Raymond Ngan Phan

Array ( [id] => 19522583 [patent_doc_number] => 12124306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Visual or acoustic project support in using an electric appliance with a battery pack [patent_app_type] => utility [patent_app_number] => 18/166157 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5302 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19706038 [patent_doc_number] => 12200090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => Multiphase clock generation with automatic skew and amplitude control [patent_app_type] => utility [patent_app_number] => 18/106047 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19267313 [patent_doc_number] => 20240211015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/105258 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19669164 [patent_doc_number] => 12181910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Timing margin sensor [patent_app_type] => utility [patent_app_number] => 18/104233 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5234 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925100 [patent_doc_number] => 20240028104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => IMPLEMENTATION OF A POWER STAGE IN A MULTI-PHASE VOLTAGE REGULATOR [patent_app_type] => utility [patent_app_number] => 18/161102 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18161102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19235909 [patent_doc_number] => 20240193104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => COMPUTER SYSTEM WITH FLEXIBLE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/156251 [patent_app_country] => US [patent_app_date] => 2023-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18156251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19283513 [patent_doc_number] => 20240219989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => System For Maintaining A Computer In An Active State [patent_app_type] => utility [patent_app_number] => 18/092293 [patent_app_country] => US [patent_app_date] => 2022-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18349397 [patent_doc_number] => 20230137508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => AREA-EFFICIENT SCALABLE MEMORY READ-DATA MULTIPLEXING AND LATCHING [patent_app_type] => utility [patent_app_number] => 18/092074 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19217 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19267321 [patent_doc_number] => 20240211023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/146811 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19267312 [patent_doc_number] => 20240211014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/146733 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19167223 [patent_doc_number] => 11983128 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-14 [patent_title] => Multidimensional and multiblock tensorized direct memory access descriptors [patent_app_type] => utility [patent_app_number] => 18/067109 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18505 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18280943 [patent_doc_number] => 20230096415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => COLLECTION OF RUNTIME INFORMATION FOR DEBUG AND ANALYSIS [patent_app_type] => utility [patent_app_number] => 18/073056 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18073056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19189988 [patent_doc_number] => 20240168901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SYSTEMS AND METHODS FOR MANAGING INFORMATION ACROSS MULTIPLE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/989446 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17989446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18734764 [patent_doc_number] => 11803495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Method for allocating addresses to a plurality of bus subscribers in a bus system that includes a master module and bus system having a master module and a plurality of bus subscribers [patent_app_type] => utility [patent_app_number] => 17/976941 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5488 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19167158 [patent_doc_number] => 11983061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-05-14 [patent_title] => Information handling system peripheral device sleep power management [patent_app_type] => utility [patent_app_number] => 17/975969 [patent_app_country] => US [patent_app_date] => 2022-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 71 [patent_no_of_words] => 15156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17975969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18346105 [patent_doc_number] => 20230134215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => System and Method for Flexibly Crossing Packets of Different Protocols [patent_app_type] => utility [patent_app_number] => 17/973894 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4891 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17973894 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18981972 [patent_doc_number] => 11907145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Integrated circuit device with multiple direct memory access (DMA) data paths [patent_app_type] => utility [patent_app_number] => 17/971707 [patent_app_country] => US [patent_app_date] => 2022-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18320822 [patent_doc_number] => 20230118950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => COMPUTER PROCESSING UNIT INTRA-FRAME CLOCK AND VOLTAGE SCALING BASED ON GRAPHICS APPLICATION AWARENESS [patent_app_type] => utility [patent_app_number] => 17/963129 [patent_app_country] => US [patent_app_date] => 2022-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17963129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20734286 [patent_doc_number] => 12641550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Dynamic power scaling in a server system using a power ramp cap [patent_app_type] => utility [patent_app_number] => 17/957376 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17957376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19933484 [patent_doc_number] => 12306688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Device state determination based on power signatures [patent_app_type] => utility [patent_app_number] => 17/934312 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 13663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934312 [rel_patent_id] =>[rel_patent_doc_number] =>)