Search

Raymond Ngan Phan

Examiner (ID: 6794)

Most Active Art Unit
2111
Art Unit(s)
2186, 2305, 2787, 2185, 2781, 2181, 2175, 2111
Total Applications
1838
Issued Applications
1676
Pending Applications
92
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18622214 [patent_doc_number] => 11755254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Network storage gateway [patent_app_type] => utility [patent_app_number] => 17/589886 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589886
Network storage gateway Jan 30, 2022 Issued
Array ( [id] => 18539520 [patent_doc_number] => 20230244628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => ADAPTIVE CHIP-TO-CHIP INTERFACE PROTOCOL ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/589633 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17589633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/589633
IC with adaptive chip-to-chip interface to support different chip-to-chip Jan 30, 2022 Issued
Array ( [id] => 17597523 [patent_doc_number] => 20220147097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SYNCHRONIZATION SIGNAL GENERATING CIRCUIT, CHIP AND SYNCHRONIZATION METHOD AND DEVICE, BASED ON MULTI-CORE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/587770 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587770
Synchronization signal generating circuit, chip and synchronization method and device, based on multi-core architecture Jan 27, 2022 Issued
Array ( [id] => 19078016 [patent_doc_number] => 11947379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Host interface to modulate a phase of a clock and system-on-chip including same [patent_app_type] => utility [patent_app_number] => 17/580861 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580861
Host interface to modulate a phase of a clock and system-on-chip including same Jan 20, 2022 Issued
Array ( [id] => 19426548 [patent_doc_number] => 12085966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Predictive open loop pre-heating of electronic devices in cold environments [patent_app_type] => utility [patent_app_number] => 17/577632 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9268 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577632
Predictive open loop pre-heating of electronic devices in cold environments Jan 17, 2022 Issued
Array ( [id] => 19327423 [patent_doc_number] => 12045106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Processing unit reset by a virtual function bypassing a host driver [patent_app_type] => utility [patent_app_number] => 17/564139 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564139 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564139
Processing unit reset by a virtual function bypassing a host driver Dec 27, 2021 Issued
Array ( [id] => 20387932 [patent_doc_number] => 12487658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Workload-dependent integrated circuit operation based on power headroom [patent_app_type] => utility [patent_app_number] => 17/559632 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559632 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559632
Workload-dependent integrated circuit operation based on power headroom Dec 21, 2021 Issued
Array ( [id] => 18454385 [patent_doc_number] => 20230195665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => SYSTEMS AND METHODS FOR HARDWARE ACCELERATION OF DATA MASKING [patent_app_type] => utility [patent_app_number] => 17/559233 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559233
Systems and methods for hardware acceleration of data masking using a field programmable gate array Dec 21, 2021 Issued
Array ( [id] => 18438305 [patent_doc_number] => 20230185600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => Time-dependent action system [patent_app_type] => utility [patent_app_number] => 17/549949 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17549949 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/549949
System to trigger time-dependent action Dec 13, 2021 Issued
Array ( [id] => 19182560 [patent_doc_number] => 11989148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Data bridge for interfacing source synchronous datapaths with unknown clock phases [patent_app_type] => utility [patent_app_number] => 17/548101 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5957 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548101
Data bridge for interfacing source synchronous datapaths with unknown clock phases Dec 9, 2021 Issued
Array ( [id] => 19293619 [patent_doc_number] => 12032973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-07-09 [patent_title] => Methods and apparatus for configuring wearable devices [patent_app_type] => utility [patent_app_number] => 17/547174 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547174 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547174
Methods and apparatus for configuring wearable devices Dec 8, 2021 Issued
Array ( [id] => 18342887 [patent_doc_number] => 11640366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-02 [patent_title] => Address decoder for a multi-chip system [patent_app_type] => utility [patent_app_number] => 17/457812 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457812 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457812
Address decoder for a multi-chip system Dec 5, 2021 Issued
Array ( [id] => 18414930 [patent_doc_number] => 11669472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Frequency translation circuitry for an interconnection in an active interposer of a semiconductor package [patent_app_type] => utility [patent_app_number] => 17/543433 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543433
Frequency translation circuitry for an interconnection in an active interposer of a semiconductor package Dec 5, 2021 Issued
Array ( [id] => 18981983 [patent_doc_number] => 11907156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => System on a chip and a power down process for IP access resilience [patent_app_type] => utility [patent_app_number] => 17/457553 [patent_app_country] => US [patent_app_date] => 2021-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17457553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/457553
System on a chip and a power down process for IP access resilience Dec 2, 2021 Issued
Array ( [id] => 18547163 [patent_doc_number] => 11720515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Article, device, and techniques for serverless stack for streaming message processing [patent_app_type] => utility [patent_app_number] => 17/530432 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530432 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530432
Article, device, and techniques for serverless stack for streaming message processing Nov 17, 2021 Issued
Array ( [id] => 18561553 [patent_doc_number] => 11726796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Platform-based enterprise technology service portfolio management [patent_app_type] => utility [patent_app_number] => 17/455544 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455544
Platform-based enterprise technology service portfolio management Nov 17, 2021 Issued
Array ( [id] => 17899358 [patent_doc_number] => 20220309020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => METHOD FOR PERFORMING DATA TRANSMISSION CONTROL OF INTER FIELD PROGRAMMABLE GATE ARRAYS AND ASSOCIATED APPARATUS [patent_app_type] => utility [patent_app_number] => 17/528125 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528125
Method for performing data transmission control of inter field programmable gate arrays and associated apparatus Nov 15, 2021 Issued
Array ( [id] => 17613890 [patent_doc_number] => 20220156170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => UNIVERSAL DEVICE IDENTIFIER SERVICE WITH ADJUSTED ATTRIBUTE DISTANCES [patent_app_type] => utility [patent_app_number] => 17/524900 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524900 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524900
Universal device identifier service with adjusted attribute distances Nov 11, 2021 Issued
Array ( [id] => 19617076 [patent_doc_number] => 20240402756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => COMPUTER SYSTEM AND CONTROL METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/699179 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18699179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/699179
COMPUTER SYSTEM AND CONTROL METHOD THEREFOR Nov 11, 2021 Pending
Array ( [id] => 17853934 [patent_doc_number] => 20220283976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => INDEPENDENT SLOT CONTROL FOR PERIPHERAL CARDS [patent_app_type] => utility [patent_app_number] => 17/524273 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524273
Slot power control for peripheral cards Nov 10, 2021 Issued
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