Rayshun K. Peng
Examiner (ID: 9441, Phone: (571)270-0194 , Office: P/3711 )
Most Active Art Unit | 3711 |
Art Unit(s) | 3711 |
Total Applications | 426 |
Issued Applications | 193 |
Pending Applications | 4 |
Abandoned Applications | 226 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17825993
[patent_doc_number] => 11430950
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-30
[patent_title] => Low resistance via contacts in a memory device
[patent_app_type] => utility
[patent_app_number] => 16/832324
[patent_app_country] => US
[patent_app_date] => 2020-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11970
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16832324
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/832324 | Low resistance via contacts in a memory device | Mar 26, 2020 | Issued |
Array
(
[id] => 16812543
[patent_doc_number] => 20210135098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => METHOD FOR FORMING MTJS WITH LITHOGRAPHY-VARIATION INDEPENDENT CRITICAL DIMENSION
[patent_app_type] => utility
[patent_app_number] => 16/826519
[patent_app_country] => US
[patent_app_date] => 2020-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10685
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826519
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/826519 | Method for forming MTJS with lithography-variation independent critical dimension | Mar 22, 2020 | Issued |
Array
(
[id] => 16488014
[patent_doc_number] => 20200381623
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-03
[patent_title] => METHODS OF FORMING SILICON NITRIDE ENCAPSULATION LAYERS
[patent_app_type] => utility
[patent_app_number] => 16/814765
[patent_app_country] => US
[patent_app_date] => 2020-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6168
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814765
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/814765 | METHODS OF FORMING SILICON NITRIDE ENCAPSULATION LAYERS | Mar 9, 2020 | Abandoned |
Array
(
[id] => 17326722
[patent_doc_number] => 11217748
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-04
[patent_title] => Semiconductor device including a data storage material pattern
[patent_app_type] => utility
[patent_app_number] => 16/807245
[patent_app_country] => US
[patent_app_date] => 2020-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 12525
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807245
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/807245 | Semiconductor device including a data storage material pattern | Mar 2, 2020 | Issued |
Array
(
[id] => 17683360
[patent_doc_number] => 11367624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-21
[patent_title] => Manufacturing method of semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/806622
[patent_app_country] => US
[patent_app_date] => 2020-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 6539
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806622
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/806622 | Manufacturing method of semiconductor device | Mar 1, 2020 | Issued |
Array
(
[id] => 16120355
[patent_doc_number] => 20200212200
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-02
[patent_title] => GATE CUT AND FIN TRIM ISOLATION FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
[patent_app_type] => utility
[patent_app_number] => 16/800860
[patent_app_country] => US
[patent_app_date] => 2020-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 73681
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800860
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/800860 | Gate cut and fin trim isolation for advanced integrated circuit structure fabrication | Feb 24, 2020 | Issued |
Array
(
[id] => 17078046
[patent_doc_number] => 11114462
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-09-07
[patent_title] => Three-dimensional memory device with composite charge storage structures and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 16/794563
[patent_app_country] => US
[patent_app_date] => 2020-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 50
[patent_no_of_words] => 21199
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794563
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/794563 | Three-dimensional memory device with composite charge storage structures and methods for forming the same | Feb 18, 2020 | Issued |
Array
(
[id] => 16973600
[patent_doc_number] => 11069580
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-20
[patent_title] => Method of manufacturing a semiconductor device including a plurality of channel patterns
[patent_app_type] => utility
[patent_app_number] => 16/793097
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 9664
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793097
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793097 | Method of manufacturing a semiconductor device including a plurality of channel patterns | Feb 17, 2020 | Issued |
Array
(
[id] => 16653467
[patent_doc_number] => 10930660
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-23
[patent_title] => Semiconductor memory device and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/793359
[patent_app_country] => US
[patent_app_date] => 2020-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 36
[patent_no_of_words] => 6737
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 330
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793359
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/793359 | Semiconductor memory device and method for manufacturing the same | Feb 17, 2020 | Issued |
Array
(
[id] => 16677821
[patent_doc_number] => 20210066587
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => DATA STORAGE STRUCTURE FOR IMPROVING MEMORY CELL RELIABILITY
[patent_app_type] => utility
[patent_app_number] => 16/788611
[patent_app_country] => US
[patent_app_date] => 2020-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9028
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788611
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/788611 | Data storage structure for improving memory cell reliability | Feb 11, 2020 | Issued |
Array
(
[id] => 18388972
[patent_doc_number] => 11659778
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-23
[patent_title] => Composite electrode material chemistry
[patent_app_type] => utility
[patent_app_number] => 16/788204
[patent_app_country] => US
[patent_app_date] => 2020-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 19238
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788204
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/788204 | Composite electrode material chemistry | Feb 10, 2020 | Issued |
Array
(
[id] => 17544354
[patent_doc_number] => 11309490
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-19
[patent_title] => Memory devices and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 16/785673
[patent_app_country] => US
[patent_app_date] => 2020-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7224
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785673
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/785673 | Memory devices and methods of forming the same | Feb 9, 2020 | Issued |
Array
(
[id] => 15823445
[patent_doc_number] => 10636922
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-04-28
[patent_title] => Trench double layer heterostructure
[patent_app_type] => utility
[patent_app_number] => 16/774353
[patent_app_country] => US
[patent_app_date] => 2020-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 4997
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774353
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/774353 | Trench double layer heterostructure | Jan 27, 2020 | Issued |
Array
(
[id] => 16981883
[patent_doc_number] => 20210226120
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => BEVEL METAL REMOVAL USING ION BEAM ETCH
[patent_app_type] => utility
[patent_app_number] => 16/748738
[patent_app_country] => US
[patent_app_date] => 2020-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3223
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16748738
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/748738 | Bevel metal removal using ion beam etch | Jan 20, 2020 | Issued |
Array
(
[id] => 17772681
[patent_doc_number] => 11404635
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-02
[patent_title] => Memory stacks and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 16/746921
[patent_app_country] => US
[patent_app_date] => 2020-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 22
[patent_no_of_words] => 9045
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746921
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/746921 | Memory stacks and methods of forming the same | Jan 18, 2020 | Issued |
Array
(
[id] => 16981537
[patent_doc_number] => 20210225774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => FOOTING FLARE PEDESTAL STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/744960
[patent_app_country] => US
[patent_app_date] => 2020-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744960
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/744960 | Footing flare pedestal structure | Jan 15, 2020 | Issued |
Array
(
[id] => 16911380
[patent_doc_number] => 11043429
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-22
[patent_title] => Semiconductor fins with dielectric isolation at fin bottom
[patent_app_type] => utility
[patent_app_number] => 16/741823
[patent_app_country] => US
[patent_app_date] => 2020-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 6589
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741823
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/741823 | Semiconductor fins with dielectric isolation at fin bottom | Jan 13, 2020 | Issued |
Array
(
[id] => 16372591
[patent_doc_number] => 10804357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-13
[patent_title] => Integration methods to fabricate internal spacers for nanowire devices
[patent_app_type] => utility
[patent_app_number] => 16/740132
[patent_app_country] => US
[patent_app_date] => 2020-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 7906
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16740132
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/740132 | Integration methods to fabricate internal spacers for nanowire devices | Jan 9, 2020 | Issued |
Array
(
[id] => 16545340
[patent_doc_number] => 20200411755
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => MEMORY CELL, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/737886
[patent_app_country] => US
[patent_app_date] => 2020-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7001
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737886
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/737886 | Memory cell, method of forming the same, and semiconductor device having the same | Jan 7, 2020 | Issued |
Array
(
[id] => 16951989
[patent_doc_number] => 20210210681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-08
[patent_title] => STRUCTURE IMPROVING RELIABILITY OF TOP ELECTRODE CONTACT FOR RESISTANCE SWITCHING RAM HAVING CELLS OF VARYING HEIGHT
[patent_app_type] => utility
[patent_app_number] => 16/733378
[patent_app_country] => US
[patent_app_date] => 2020-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7915
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16733378
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/733378 | Structure improving reliability of top electrode contact for resistance switching RAM having cells of varying height | Jan 2, 2020 | Issued |