Search

Rayshun K. Peng

Examiner (ID: 9441, Phone: (571)270-0194 , Office: P/3711 )

Most Active Art Unit
3711
Art Unit(s)
3711
Total Applications
426
Issued Applications
193
Pending Applications
4
Abandoned Applications
226

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15760643 [patent_doc_number] => 10622453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Vertical MOS transistor [patent_app_type] => utility [patent_app_number] => 16/390210 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 28 [patent_no_of_words] => 4528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390210 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390210
Vertical MOS transistor Apr 21, 2019 Issued
Array ( [id] => 15000461 [patent_doc_number] => 20190319188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => NANO MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/381641 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381641 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381641
Nano memory device Apr 10, 2019 Issued
Array ( [id] => 16172878 [patent_doc_number] => 10714456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Dual sided fan-out package having low warpage across all temperatures [patent_app_type] => utility [patent_app_number] => 16/379078 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 7401 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/379078
Dual sided fan-out package having low warpage across all temperatures Apr 8, 2019 Issued
Array ( [id] => 14676797 [patent_doc_number] => 20190237513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SOLID STATE IMAGE SENSOR, PRODUCTION METHOD THEREOF AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/378339 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378339 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378339
Solid state image sensor, production method thereof and electronic device Apr 7, 2019 Issued
Array ( [id] => 16845936 [patent_doc_number] => 11018032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => High pressure and high temperature anneal chamber [patent_app_type] => utility [patent_app_number] => 16/378140 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7202 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378140 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378140
High pressure and high temperature anneal chamber Apr 7, 2019 Issued
Array ( [id] => 15580931 [patent_doc_number] => 10580860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Integration methods to fabricate internal spacers for nanowire devices [patent_app_type] => utility [patent_app_number] => 16/358613 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7879 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358613
Integration methods to fabricate internal spacers for nanowire devices Mar 18, 2019 Issued
Array ( [id] => 16332657 [patent_doc_number] => 20200303623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => INTERCONNECT STRUCTURES FOR LOGIC AND MEMORY DEVICES AND METHODS OF FABRICATION [patent_app_type] => utility [patent_app_number] => 16/358671 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/358671
Interconnect structures for logic and memory devices and methods of fabrication Mar 18, 2019 Issued
Array ( [id] => 17210877 [patent_doc_number] => 11171256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Process for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters [patent_app_type] => utility [patent_app_number] => 16/352029 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 8760 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352029 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352029
Process for manufacturing a plurality of crystalline semiconductor islands having a variety of lattice parameters Mar 12, 2019 Issued
Array ( [id] => 14573581 [patent_doc_number] => 20190214398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => STACKED FINFET EEPROM [patent_app_type] => utility [patent_app_number] => 16/352222 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352222
Stacked FinFET EEPROM Mar 12, 2019 Issued
Array ( [id] => 17032771 [patent_doc_number] => 11094589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Multicolor self-aligned contact selective etch [patent_app_type] => utility [patent_app_number] => 16/299766 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4567 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299766
Multicolor self-aligned contact selective etch Mar 11, 2019 Issued
Array ( [id] => 17002519 [patent_doc_number] => 11081341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Apparatus for fabricating a semiconductor device with target sputtering and target sputtering method for fabricating the semiconductor device [patent_app_type] => utility [patent_app_number] => 16/299987 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299987 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299987
Apparatus for fabricating a semiconductor device with target sputtering and target sputtering method for fabricating the semiconductor device Mar 11, 2019 Issued
Array ( [id] => 15564921 [patent_doc_number] => 20200066872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE WITH INNER SPACER LAYER [patent_app_type] => utility [patent_app_number] => 16/299531 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299531
Method for forming semiconductor device structure with inner spacer layer Mar 11, 2019 Issued
Array ( [id] => 16316114 [patent_doc_number] => 20200294852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => Methods Of Forming Conductive Vias And Methods Of Forming Memory Circuitry [patent_app_type] => utility [patent_app_number] => 16/299469 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16299469 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/299469
Methods of forming conductive vias and methods of forming memory circuitry Mar 11, 2019 Issued
Array ( [id] => 16448154 [patent_doc_number] => 10840085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Method for improving bonding of dangling bonds of silicon atoms [patent_app_type] => utility [patent_app_number] => 16/351407 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2484 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16351407 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/351407
Method for improving bonding of dangling bonds of silicon atoms Mar 11, 2019 Issued
Array ( [id] => 18088849 [patent_doc_number] => 11538988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Memory device with multi-layer liner structure [patent_app_type] => utility [patent_app_number] => 16/295671 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11565 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295671 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/295671
Memory device with multi-layer liner structure Mar 6, 2019 Issued
Array ( [id] => 16301284 [patent_doc_number] => 20200287007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH A SILICON CARBON NITRIDE INTERFACIAL LAYER IN A CHARGE STORAGE LAYER AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 16/291220 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291220 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291220
Three-dimensional memory device with a silicon carbon nitride interfacial layer in a charge storage layer and methods of making the same Mar 3, 2019 Issued
Array ( [id] => 16668541 [patent_doc_number] => 10937799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/291120 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 43 [patent_no_of_words] => 5496 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291120 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291120
Semiconductor device and method of manufacturing the same Mar 3, 2019 Issued
Array ( [id] => 17284067 [patent_doc_number] => 11201108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Semiconductor package mounted substrate [patent_app_type] => utility [patent_app_number] => 16/291060 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 29 [patent_no_of_words] => 11112 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291060 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291060
Semiconductor package mounted substrate Mar 3, 2019 Issued
Array ( [id] => 15503601 [patent_doc_number] => 20200051989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/291107 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291107 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291107
Semiconductor device Mar 3, 2019 Issued
Array ( [id] => 16020985 [patent_doc_number] => 20200185336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => INTEGRATED CIRCUIT WITH INDUCTORS HAVING ELECTRICALLY SPLIT SCRIBE SEAL [patent_app_type] => utility [patent_app_number] => 16/291042 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291042 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291042
Integrated circuit with inductors having electrically split scribe seal Mar 3, 2019 Issued
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