Search

Rayshun K. Peng

Examiner (ID: 9441, Phone: (571)270-0194 , Office: P/3711 )

Most Active Art Unit
3711
Art Unit(s)
3711
Total Applications
426
Issued Applications
193
Pending Applications
4
Abandoned Applications
226

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14920647 [patent_doc_number] => 10431651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-01 [patent_title] => Nanosheet transistor with robust source/drain isolation from substrate [patent_app_type] => utility [patent_app_number] => 15/967524 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15967524 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/967524
Nanosheet transistor with robust source/drain isolation from substrate Apr 29, 2018 Issued
Array ( [id] => 13392695 [patent_doc_number] => 20180247890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => Semiconductor Structure and Manufacturing Method Thereof [patent_app_type] => utility [patent_app_number] => 15/964453 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964453 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964453
Semiconductor structure and manufacturing method thereof Apr 26, 2018 Issued
Array ( [id] => 16280263 [patent_doc_number] => 10763304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Semiconductor structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 15/960238 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8200 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960238 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960238
Semiconductor structure and method of forming the same Apr 22, 2018 Issued
Array ( [id] => 15030485 [patent_doc_number] => 20190326247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => BOND WIRE SUPPORT SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 15/960093 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960093 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960093
Bond wire support systems and methods Apr 22, 2018 Issued
Array ( [id] => 16536599 [patent_doc_number] => 10879212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Processed stacked dies [patent_app_type] => utility [patent_app_number] => 15/960179 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7231 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960179
Processed stacked dies Apr 22, 2018 Issued
Array ( [id] => 15030427 [patent_doc_number] => 20190326218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => 3D NAND WORD LINE CONNECTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/960106 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960106 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960106
3D NAND world line connection structure Apr 22, 2018 Issued
Array ( [id] => 15030479 [patent_doc_number] => 20190326244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/960222 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960222 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960222
Semiconductor structure and manufacturing method thereof Apr 22, 2018 Issued
Array ( [id] => 13363743 [patent_doc_number] => 20180233411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-16 [patent_title] => SEMICONDUCTOR DIE SINGULATION METHODS [patent_app_type] => utility [patent_app_number] => 15/955581 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15955581 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/955581
Semiconductor die singulation methods Apr 16, 2018 Issued
Array ( [id] => 14969073 [patent_doc_number] => 20190312015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => LED BACKPLANE HAVING PLANAR BONDING SURFACES AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/949514 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949514 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949514
LED backplane having planar bonding surfaces and method of making thereof Apr 9, 2018 Issued
Array ( [id] => 14968953 [patent_doc_number] => 20190311955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => SEMICONDUCTOR FINS WITH DIELECTRIC ISOLATION AT FIN BOTTOM [patent_app_type] => utility [patent_app_number] => 15/949602 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949602 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949602
Semiconductor fins with dielectric isolation at fin bottom Apr 9, 2018 Issued
Array ( [id] => 16280184 [patent_doc_number] => 10763225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Antenna module [patent_app_type] => utility [patent_app_number] => 15/949439 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 38 [patent_no_of_words] => 9381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949439
Antenna module Apr 9, 2018 Issued
Array ( [id] => 16132811 [patent_doc_number] => 10700173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => FinFET device with a wrap-around silicide source/drain contact structure [patent_app_type] => utility [patent_app_number] => 15/949730 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5963 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949730 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949730
FinFET device with a wrap-around silicide source/drain contact structure Apr 9, 2018 Issued
Array ( [id] => 15192185 [patent_doc_number] => 10493567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Solder alloy and bonded structure using the same [patent_app_type] => utility [patent_app_number] => 15/949360 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7881 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949360
Solder alloy and bonded structure using the same Apr 9, 2018 Issued
Array ( [id] => 14509507 [patent_doc_number] => 20190198408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => DISPLAY PANEL AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/301911 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16301911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/301911
Display panel and display apparatus Mar 22, 2018 Issued
Array ( [id] => 16293562 [patent_doc_number] => 10770417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Chip packages and methods for forming the same [patent_app_type] => utility [patent_app_number] => 15/916286 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2832 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916286
Chip packages and methods for forming the same Mar 8, 2018 Issued
Array ( [id] => 15823391 [patent_doc_number] => 10636894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Fin-type transistors with spacers on the gates [patent_app_type] => utility [patent_app_number] => 15/916323 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 50 [patent_no_of_words] => 5090 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916323 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916323
Fin-type transistors with spacers on the gates Mar 8, 2018 Issued
Array ( [id] => 14317569 [patent_doc_number] => 20190148488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/916355 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916355
Semiconductor device Mar 8, 2018 Issued
Array ( [id] => 13485795 [patent_doc_number] => 20180294440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => DISPLAY DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 15/916369 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916369 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916369
Display device and manufacturing method of the same Mar 8, 2018 Issued
Array ( [id] => 13159769 [patent_doc_number] => 10096620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Electrical connection structure and thin film transistor array substrate including electrical connection structure [patent_app_type] => utility [patent_app_number] => 15/916476 [patent_app_country] => US [patent_app_date] => 2018-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5178 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15916476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/916476
Electrical connection structure and thin film transistor array substrate including electrical connection structure Mar 8, 2018 Issued
Array ( [id] => 15200645 [patent_doc_number] => 10497828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Light-emitting devices and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/906539 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 13296 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906539 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906539
Light-emitting devices and methods of manufacturing the same Feb 26, 2018 Issued
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