Search

Rayshun K. Peng

Examiner (ID: 9441, Phone: (571)270-0194 , Office: P/3711 )

Most Active Art Unit
3711
Art Unit(s)
3711
Total Applications
426
Issued Applications
193
Pending Applications
4
Abandoned Applications
226

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15669641 [patent_doc_number] => 10599045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Exposure method, exposure system, and manufacturing method for semiconductor device [patent_app_type] => utility [patent_app_number] => 15/903274 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 6184 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903274 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903274
Exposure method, exposure system, and manufacturing method for semiconductor device Feb 22, 2018 Issued
Array ( [id] => 15955187 [patent_doc_number] => 10665507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Automated transfer and drying tool for process chamber [patent_app_type] => utility [patent_app_number] => 15/903815 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903815
Automated transfer and drying tool for process chamber Feb 22, 2018 Issued
Array ( [id] => 14509331 [patent_doc_number] => 20190198320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => Methods Of Forming A Channel Region Of A Transistor And Methods Used In Forming A Memory Array [patent_app_type] => utility [patent_app_number] => 15/903280 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903280
Methods of forming a channel region of a transistor and methods used in forming a memory array Feb 22, 2018 Issued
Array ( [id] => 13405357 [patent_doc_number] => 20180254221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => APPARATUS AND METHOD FOR WAFER THINNING IN ADVANCED PACKAGING APPLICATIONS [patent_app_type] => utility [patent_app_number] => 15/903799 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903799 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903799
Apparatus and method for wafer thinning in advanced packaging applications Feb 22, 2018 Issued
Array ( [id] => 16068197 [patent_doc_number] => 10693065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Tapered cell profile and fabrication [patent_app_type] => utility [patent_app_number] => 15/893100 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 14207 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15893100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/893100
Tapered cell profile and fabrication Feb 8, 2018 Issued
Array ( [id] => 15401403 [patent_doc_number] => 10541364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Memory cells with asymmetrical electrode interfaces [patent_app_type] => utility [patent_app_number] => 15/893108 [patent_app_country] => US [patent_app_date] => 2018-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 21523 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15893108 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/893108
Memory cells with asymmetrical electrode interfaces Feb 8, 2018 Issued
Array ( [id] => 14031903 [patent_doc_number] => 10227693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-12 [patent_title] => Outgassing impact on process chamber reduction via chamber pump and purge [patent_app_type] => utility [patent_app_number] => 15/884492 [patent_app_country] => US [patent_app_date] => 2018-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6520 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884492
Outgassing impact on process chamber reduction via chamber pump and purge Jan 30, 2018 Issued
Array ( [id] => 14656511 [patent_doc_number] => 20190235384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => TEMPERATURE CONTROLLING APPARATUS AND METHOD FOR FORMING COATING LAYER [patent_app_type] => utility [patent_app_number] => 15/884299 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15884299 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/884299
Temperature controlling apparatus and method for forming coating layer Jan 29, 2018 Issued
Array ( [id] => 16372311 [patent_doc_number] => 10804077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Microwave plasma source, microwave plasma processing apparatus and plasma processing method [patent_app_type] => utility [patent_app_number] => 15/883670 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883670 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883670
Microwave plasma source, microwave plasma processing apparatus and plasma processing method Jan 29, 2018 Issued
Array ( [id] => 14079959 [patent_doc_number] => 20190088867 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2019-03-21 [patent_title] => PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS [patent_app_type] => utility [patent_app_number] => 15/882666 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882666
Phase change memory stack with treated sidewalls Jan 28, 2018 Issued
Array ( [id] => 12779839 [patent_doc_number] => 20180151781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => LIGHT EMITTING DEVICE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/881802 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881802 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881802
LIGHT EMITTING DEVICE PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Jan 28, 2018 Abandoned
Array ( [id] => 14079959 [patent_doc_number] => 20190088867 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2019-03-21 [patent_title] => PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS [patent_app_type] => utility [patent_app_number] => 15/882666 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15882666 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/882666
Phase change memory stack with treated sidewalls Jan 28, 2018 Issued
Array ( [id] => 14920525 [patent_doc_number] => 10431590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Semiconductor memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/863490 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 36 [patent_no_of_words] => 6697 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863490
Semiconductor memory device and method for manufacturing the same Jan 4, 2018 Issued
Array ( [id] => 14011747 [patent_doc_number] => 10224349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-05 [patent_title] => Method of manufacturing TFT array substrate and display device [patent_app_type] => utility [patent_app_number] => 15/743292 [patent_app_country] => US [patent_app_date] => 2018-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3274 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15743292 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/743292
Method of manufacturing TFT array substrate and display device Jan 3, 2018 Issued
Array ( [id] => 13951223 [patent_doc_number] => 10211395 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-19 [patent_title] => Method for combining NVM class and SRAM class MRAM elements on the same chip [patent_app_type] => utility [patent_app_number] => 15/859451 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859451 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859451
Method for combining NVM class and SRAM class MRAM elements on the same chip Dec 29, 2017 Issued
Array ( [id] => 14382097 [patent_doc_number] => 20190164961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => FIN END PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 15/859351 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859351 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859351
Fin end plug structures for advanced integrated circuit structure fabrication Dec 29, 2017 Issued
Array ( [id] => 14738897 [patent_doc_number] => 10388860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Method for manufacturing high density magnetic random access memory devices using diamond like carbon hard mask [patent_app_type] => utility [patent_app_number] => 15/859459 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5910 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859459
Method for manufacturing high density magnetic random access memory devices using diamond like carbon hard mask Dec 29, 2017 Issued
Array ( [id] => 16249469 [patent_doc_number] => 10748844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Stress isolation for silicon photonic applications [patent_app_type] => utility [patent_app_number] => 15/859331 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7790 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859331 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859331
Stress isolation for silicon photonic applications Dec 29, 2017 Issued
Array ( [id] => 14542291 [patent_doc_number] => 20190206767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => DUAL-DAMASCENE ZERO-MISALIGNMENT-VIA PROCESS FOR SEMICONDUCTOR PACKAGING [patent_app_type] => utility [patent_app_number] => 15/859332 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859332
Dual-damascene zero-misalignment-via process for semiconductor packaging Dec 29, 2017 Issued
Array ( [id] => 14366819 [patent_doc_number] => 10304721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-28 [patent_title] => Formation of isolation layers using a dry-wet-dry oxidation technique [patent_app_type] => utility [patent_app_number] => 15/859447 [patent_app_country] => US [patent_app_date] => 2017-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3892 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859447 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859447
Formation of isolation layers using a dry-wet-dry oxidation technique Dec 29, 2017 Issued
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