Razu A Miah
Examiner (ID: 13820)
Most Active Art Unit | 2441 |
Art Unit(s) | 2441 |
Total Applications | 483 |
Issued Applications | 396 |
Pending Applications | 17 |
Abandoned Applications | 68 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 9515313
[patent_doc_number] => 20140151805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-05
[patent_title] => 'METHOD FOR FABRICATING A CONNECTION REGION IN A SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/888307
[patent_app_country] => US
[patent_app_date] => 2013-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3692
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13888307
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/888307 | Method for fabricating a connection region in a semiconductor device | May 5, 2013 | Issued |
Array
(
[id] => 9013870
[patent_doc_number] => 20130228833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-05
[patent_title] => 'SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 13/848707
[patent_app_country] => US
[patent_app_date] => 2013-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 47
[patent_figures_cnt] => 47
[patent_no_of_words] => 17257
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13848707
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/848707 | System and method for integrated circuits with cylindrical gate structures | Mar 20, 2013 | Issued |
Array
(
[id] => 8916438
[patent_doc_number] => 20130178062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => '3D IC METHOD AND DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/783553
[patent_app_country] => US
[patent_app_date] => 2013-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 20526
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783553
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/783553 | 3D IC method and device | Mar 3, 2013 | Issued |
Array
(
[id] => 8916411
[patent_doc_number] => 20130178036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/783296
[patent_app_country] => US
[patent_app_date] => 2013-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6474
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783296
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/783296 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | Mar 2, 2013 | Abandoned |
Array
(
[id] => 8916407
[patent_doc_number] => 20130178032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-11
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/783299
[patent_app_country] => US
[patent_app_date] => 2013-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6464
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783299
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/783299 | Semiconductor device and method for manufacturing semiconductor device | Mar 2, 2013 | Issued |
Array
(
[id] => 8866134
[patent_doc_number] => 20130149837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/758802
[patent_app_country] => US
[patent_app_date] => 2013-02-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 7633
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758802
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/758802 | Semiconductor device and method of manufacturing the same | Feb 3, 2013 | Issued |
Array
(
[id] => 9662171
[patent_doc_number] => 08809146
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Semiconductor devices comprising a plurality of gate structures'
[patent_app_type] => utility
[patent_app_number] => 13/751679
[patent_app_country] => US
[patent_app_date] => 2013-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 5954
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13751679
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/751679 | Semiconductor devices comprising a plurality of gate structures | Jan 27, 2013 | Issued |
Array
(
[id] => 10179062
[patent_doc_number] => 09209277
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-12-08
[patent_title] => 'Manufacturing methods for laterally diffused metal oxide semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 13/747608
[patent_app_country] => US
[patent_app_date] => 2013-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7746
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13747608
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/747608 | Manufacturing methods for laterally diffused metal oxide semiconductor devices | Jan 22, 2013 | Issued |
Array
(
[id] => 8818345
[patent_doc_number] => 20130119390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'THIN FILM TRANSISTOR SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/735501
[patent_app_country] => US
[patent_app_date] => 2013-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5367
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735501
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/735501 | Thin film transistor substrate | Jan 6, 2013 | Issued |
Array
(
[id] => 9350259
[patent_doc_number] => 08669150
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-11
[patent_title] => 'Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 13/724307
[patent_app_country] => US
[patent_app_date] => 2012-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 4100
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13724307
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/724307 | Semiconductor device with reliable high-voltage gate oxide and method of manufacture thereof | Dec 20, 2012 | Issued |
Array
(
[id] => 8789023
[patent_doc_number] => 20130105992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-02
[patent_title] => 'SEMICONDUCTOR COMPONENT HAVING A STACK OF SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/721957
[patent_app_country] => US
[patent_app_date] => 2012-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4810
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13721957
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/721957 | SEMICONDUCTOR COMPONENT HAVING A STACK OF SEMICONDUCTOR CHIPS AND METHOD FOR PRODUCING THE SAME | Dec 19, 2012 | Abandoned |
Array
(
[id] => 8753619
[patent_doc_number] => 20130087923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-11
[patent_title] => 'MULTI COMPONENT DIELECTRIC LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/691129
[patent_app_country] => US
[patent_app_date] => 2012-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6315
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691129
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/691129 | Multi component dielectric layer | Nov 29, 2012 | Issued |
Array
(
[id] => 8765005
[patent_doc_number] => 20130093042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-18
[patent_title] => 'TSV Formation Processes Using TSV-Last Approach'
[patent_app_type] => utility
[patent_app_number] => 13/691178
[patent_app_country] => US
[patent_app_date] => 2012-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2187
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691178
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/691178 | TSV formation processes using TSV-last approach | Nov 29, 2012 | Issued |
Array
(
[id] => 10402799
[patent_doc_number] => 20150287808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-08
[patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/435616
[patent_app_country] => US
[patent_app_date] => 2012-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2823
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14435616
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/435616 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | Oct 24, 2012 | Abandoned |
Array
(
[id] => 10106648
[patent_doc_number] => 09142431
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-09-22
[patent_title] => 'Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking'
[patent_app_type] => utility
[patent_app_number] => 13/622297
[patent_app_country] => US
[patent_app_date] => 2012-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 39
[patent_no_of_words] => 6764
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 37
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13622297
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/622297 | Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking | Sep 17, 2012 | Issued |
Array
(
[id] => 8603922
[patent_doc_number] => 20130009234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-10
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/620767
[patent_app_country] => US
[patent_app_date] => 2012-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2923
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13620767
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/620767 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Sep 14, 2012 | Abandoned |
Array
(
[id] => 8647136
[patent_doc_number] => 20130032866
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-07
[patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/618219
[patent_app_country] => US
[patent_app_date] => 2012-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 18517
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13618219
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/618219 | Semiconductor device and manufacturing method thereof | Sep 13, 2012 | Issued |
Array
(
[id] => 9236817
[patent_doc_number] => RE044630
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2013-12-10
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => reissue
[patent_app_number] => 13/616208
[patent_app_country] => US
[patent_app_date] => 2012-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 3410
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616208
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/616208 | Semiconductor device and method for manufacturing the same | Sep 13, 2012 | Issued |
Array
(
[id] => 8610116
[patent_doc_number] => 20130015428
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-17
[patent_title] => 'Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control'
[patent_app_type] => utility
[patent_app_number] => 13/610089
[patent_app_country] => US
[patent_app_date] => 2012-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3928
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610089
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/610089 | Vertical stacking of carbon nanotube arrays for current enhancement and control | Sep 10, 2012 | Issued |
Array
(
[id] => 8582952
[patent_doc_number] => 20130001773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump'
[patent_app_type] => utility
[patent_app_number] => 13/609003
[patent_app_country] => US
[patent_app_date] => 2012-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8871
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13609003
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/609003 | Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump | Sep 9, 2012 | Abandoned |