Search

Reba I. Elmore

Examiner (ID: 18797, Phone: (571)272-4192 , Office: P/2131 )

Most Active Art Unit
2189
Art Unit(s)
2187, 2131, 2312, 2759, 2786, 2189, 2318
Total Applications
1195
Issued Applications
971
Pending Applications
19
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8325740 [patent_doc_number] => 20120198141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY' [patent_app_type] => utility [patent_app_number] => 13/443121 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 14173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443121 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443121
Integrating data from symmetric and asymmetric memory Apr 9, 2012 Issued
Array ( [id] => 8325733 [patent_doc_number] => 20120198142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'SYSTEM AND APPARATUS FOR FLASH MEMORY DATA MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/443342 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3849 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443342 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443342
System and apparatus for flash memory data management Apr 9, 2012 Issued
Array ( [id] => 11795872 [patent_doc_number] => 09405701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Apparatus and method for accelerating operations in a processor which uses shared virtual memory' [patent_app_type] => utility [patent_app_number] => 13/994577 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9449 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994577 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994577
Apparatus and method for accelerating operations in a processor which uses shared virtual memory Mar 29, 2012 Issued
Array ( [id] => 9056773 [patent_doc_number] => 20130254487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'METHOD FOR ACCESSING MIRRORED SHARED MEMORIES AND STORAGE SUBSYSTEM USING METHOD FOR ACCESSING MIRRORED SHARED MEMORIES' [patent_app_type] => utility [patent_app_number] => 13/501022 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 15230 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13501022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/501022
Method for accessing mirrored shared memories and storage subsystem using method for accessing mirrored shared memories Mar 22, 2012 Issued
Array ( [id] => 9169752 [patent_doc_number] => 08595445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Non-volatile memory and method with host controlled caching' [patent_app_type] => utility [patent_app_number] => 13/419733 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5292 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419733
Non-volatile memory and method with host controlled caching Mar 13, 2012 Issued
Array ( [id] => 8899415 [patent_doc_number] => 08478949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same' [patent_app_type] => utility [patent_app_number] => 13/418810 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7023 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418810 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418810
Data accessing method for flash memory storage device having data perturbation module, and storage system and controller using the same Mar 12, 2012 Issued
Array ( [id] => 9023389 [patent_doc_number] => 08533386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-10 [patent_title] => 'Modifying data stored in flash memory' [patent_app_type] => utility [patent_app_number] => 13/406756 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406756 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406756
Modifying data stored in flash memory Feb 27, 2012 Issued
Array ( [id] => 9193385 [patent_doc_number] => 20130332700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'Cloud Storage Arrangement and Method of Operating Thereof' [patent_app_type] => utility [patent_app_number] => 14/000889 [patent_app_country] => US [patent_app_date] => 2012-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8875 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14000889 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/000889
Storage arrangement and method using a plurality of storage spaces which have separate control layers and separate mapping structures Feb 21, 2012 Issued
Array ( [id] => 8945936 [patent_doc_number] => 08499123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-30 [patent_title] => 'Multi-stage pipeline for cache access' [patent_app_type] => utility [patent_app_number] => 13/357787 [patent_app_country] => US [patent_app_date] => 2012-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14576 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13357787 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357787
Multi-stage pipeline for cache access Jan 24, 2012 Issued
Array ( [id] => 8291547 [patent_doc_number] => 20120179875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'USING EPHEMERAL STORES FOR FINE-GRAINED CONFLICT DETECTION IN A HARDWARE ACCELERATED STM' [patent_app_type] => utility [patent_app_number] => 13/346987 [patent_app_country] => US [patent_app_date] => 2012-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7040 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13346987 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/346987
Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM Jan 9, 2012 Issued
Array ( [id] => 8189127 [patent_doc_number] => 20120117319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'LOW POWER, HASH-CONTENT ADDRESSABLE MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/345530 [patent_app_country] => US [patent_app_date] => 2012-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7465 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117319.pdf [firstpage_image] =>[orig_patent_app_number] => 13345530 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/345530
Low power, hash-content addressable memory architecture Jan 5, 2012 Issued
Array ( [id] => 8176563 [patent_doc_number] => 20120110289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DATA BACKUP SYSTEM AND METHOD FOR VIRTUAL INFRASTRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/344501 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110289.pdf [firstpage_image] =>[orig_patent_app_number] => 13344501 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/344501
Data backup system and method for virtual infrastructure Jan 4, 2012 Issued
Array ( [id] => 9992583 [patent_doc_number] => 09037804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Efficient support of sparse data structure access' [patent_app_type] => utility [patent_app_number] => 13/995209 [patent_app_country] => US [patent_app_date] => 2011-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4885 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13995209 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/995209
Efficient support of sparse data structure access Dec 28, 2011 Issued
Array ( [id] => 8899396 [patent_doc_number] => 08478930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Solid state drive power safe wear-leveling' [patent_app_type] => utility [patent_app_number] => 13/335194 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335194 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335194
Solid state drive power safe wear-leveling Dec 21, 2011 Issued
Array ( [id] => 10562528 [patent_doc_number] => 09286205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Apparatus and method for phase change memory drift management' [patent_app_type] => utility [patent_app_number] => 13/994116 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 21464 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13994116 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/994116
Apparatus and method for phase change memory drift management Dec 19, 2011 Issued
Array ( [id] => 8882604 [patent_doc_number] => 20130155788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'DDR 2D VREF TRAINING' [patent_app_type] => utility [patent_app_number] => 13/330460 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8329 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13330460 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/330460
DDR 2D Vref training Dec 18, 2011 Issued
Array ( [id] => 9781247 [patent_doc_number] => 08856468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Memory device capable of improving write processing speed and memory control method' [patent_app_type] => utility [patent_app_number] => 13/278973 [patent_app_country] => US [patent_app_date] => 2011-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5886 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13278973 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/278973
Memory device capable of improving write processing speed and memory control method Oct 20, 2011 Issued
Array ( [id] => 8757026 [patent_doc_number] => 20130091331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO MANAGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/270785 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13463 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13270785 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/270785
METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO MANAGE MEMORY Oct 10, 2011 Abandoned
Array ( [id] => 9611566 [patent_doc_number] => 08788755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Mass data storage system and method of operating thereof' [patent_app_type] => utility [patent_app_number] => 13/270725 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11096 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13270725 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/270725
Mass data storage system and method of operating thereof Oct 10, 2011 Issued
Array ( [id] => 8757013 [patent_doc_number] => 20130091318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'SYSTEM AND METHOD FOR CRITICAL ADDRESS SPACE PROTECTION IN A HYPERVISOR ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/271102 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13271102 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/271102
System and method for critical address space protection in a hypervisor environment Oct 10, 2011 Issued
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