Search

Rebecca Straszheim Preston

Examiner (ID: 18724, Phone: (571)270-5233 , Office: P/3738 )

Most Active Art Unit
3774
Art Unit(s)
3738, 3774
Total Applications
670
Issued Applications
462
Pending Applications
66
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19407313 [patent_doc_number] => 20240290824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/657385 [patent_app_country] => US [patent_app_date] => 2024-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18657385 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/657385
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF May 6, 2024 Pending
Array ( [id] => 19515651 [patent_doc_number] => 20240347337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => LOW-K ALD GAP-FILL METHODS AND MATERIAL [patent_app_type] => utility [patent_app_number] => 18/656209 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18656209 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/656209
LOW-K ALD GAP-FILL METHODS AND MATERIAL May 5, 2024 Pending
Array ( [id] => 19407109 [patent_doc_number] => 20240290620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => CUT METAL GATE PROCESSES [patent_app_type] => utility [patent_app_number] => 18/638112 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638112 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638112
CUT METAL GATE PROCESSES Apr 16, 2024 Pending
Array ( [id] => 19361267 [patent_doc_number] => 20240263301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => CHAMFER-LESS VIA INTEGRATION SCHEME [patent_app_type] => utility [patent_app_number] => 18/634426 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634426
CHAMFER-LESS VIA INTEGRATION SCHEME Apr 11, 2024 Pending
Array ( [id] => 19365671 [patent_doc_number] => 20240267705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/591665 [patent_app_country] => US [patent_app_date] => 2024-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18591665 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/591665
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM Feb 28, 2024 Abandoned
Array ( [id] => 19071316 [patent_doc_number] => 20240105742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => IMAGING ELEMENT AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/529579 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529579
Imaging element and electronic apparatus Dec 4, 2023 Issued
Array ( [id] => 20276490 [patent_doc_number] => 12446279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Semiconductor device having 2D channel layer [patent_app_type] => utility [patent_app_number] => 18/515148 [patent_app_country] => US [patent_app_date] => 2023-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 87 [patent_no_of_words] => 7259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18515148 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/515148
Semiconductor device having 2D channel layer Nov 19, 2023 Issued
Array ( [id] => 19116571 [patent_doc_number] => 20240128321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING BLOCKING LAYER AND SOURCE/DRAIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/378874 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378874 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378874
SEMICONDUCTOR DEVICE INCLUDING BLOCKING LAYER AND SOURCE/DRAIN STRUCTURE Oct 10, 2023 Pending
Array ( [id] => 19611044 [patent_doc_number] => 12159926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Lateral bipolar transistor [patent_app_type] => utility [patent_app_number] => 18/373598 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3593 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18373598 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/373598
Lateral bipolar transistor Sep 26, 2023 Issued
Array ( [id] => 19850774 [patent_doc_number] => 20250096125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => ANTIFUSE AND RESISTOR [patent_app_type] => utility [patent_app_number] => 18/470472 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18470472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/470472
ANTIFUSE AND RESISTOR Sep 19, 2023 Pending
Array ( [id] => 18898784 [patent_doc_number] => 20240014269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/471282 [patent_app_country] => US [patent_app_date] => 2023-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471282 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471282
Semiconductor device Sep 19, 2023 Issued
Array ( [id] => 18883148 [patent_doc_number] => 20240006517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => TRANSISTOR WITH WRAP-AROUND EXTRINSIC BASE [patent_app_type] => utility [patent_app_number] => 18/370001 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18370001 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/370001
Transistor with wrap-around extrinsic base Sep 18, 2023 Issued
Array ( [id] => 18883008 [patent_doc_number] => 20240006377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER [patent_app_type] => utility [patent_app_number] => 18/467481 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467481 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/467481
MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTED WAFER Sep 13, 2023 Pending
Array ( [id] => 19146502 [patent_doc_number] => 20240145532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => COMBINED CHARGE BALANCE AND EDGE TERMINATION SURFACE PASSIVATION FOR A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/464686 [patent_app_country] => US [patent_app_date] => 2023-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/464686
COMBINED CHARGE BALANCE AND EDGE TERMINATION SURFACE PASSIVATION FOR A SEMICONDUCTOR DEVICE AND METHODS OF FABRICATING THE SAME Sep 10, 2023 Pending
Array ( [id] => 19071418 [patent_doc_number] => 20240105844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => NATIVE NMOS DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/462803 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462803
NATIVE NMOS DEVICE AND MANUFACTURING METHOD THEREOF Sep 6, 2023 Pending
Array ( [id] => 19271632 [patent_doc_number] => 20240215339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/455666 [patent_app_country] => US [patent_app_date] => 2023-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18455666 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/455666
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME Aug 24, 2023 Pending
Array ( [id] => 18866171 [patent_doc_number] => 20230420608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => ALL-NITRIDE-BASED EPITAXIAL STRUCTURE AND LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/236413 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236413 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/236413
ALL-NITRIDE-BASED EPITAXIAL STRUCTURE AND LIGHT-EMITTING DEVICE Aug 21, 2023 Pending
Array ( [id] => 19161282 [patent_doc_number] => 20240153989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/453932 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18453932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/453932
SEMICONDUCTOR DEVICE Aug 21, 2023 Pending
Array ( [id] => 19788556 [patent_doc_number] => 20250062235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => PACKAGE SUBSTRATE WITH METALLIZATION LAYER(S) THAT INCLUDES AN ADDITIONAL METAL PAD LAYER TO FACILITATE REDUCED VIA SIZE FOR REDUCED BUMP PITCH, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 18/450636 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/450636
PACKAGE SUBSTRATE WITH METALLIZATION LAYER(S) THAT INCLUDES AN ADDITIONAL METAL PAD LAYER TO FACILITATE REDUCED VIA SIZE FOR REDUCED BUMP PITCH, AND RELATED INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS Aug 15, 2023 Pending
Array ( [id] => 19790091 [patent_doc_number] => 20250063770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/451096 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451096
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE Aug 15, 2023 Pending
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