Search

Redhwan K. Mawari

Examiner (ID: 12909, Phone: (571)270-1535 , Office: P/3665 )

Most Active Art Unit
3665
Art Unit(s)
3663, 3665, 3662, 3667
Total Applications
902
Issued Applications
663
Pending Applications
71
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17002350 [patent_doc_number] => 11081172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-03 [patent_title] => On-chip security key with phase change memory [patent_app_type] => utility [patent_app_number] => 16/838157 [patent_app_country] => US [patent_app_date] => 2020-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16838157 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/838157
On-chip security key with phase change memory Apr 1, 2020 Issued
Array ( [id] => 16226035 [patent_doc_number] => 20200251152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-06 [patent_title] => METHOD, SYSTEM AND DEVICE FOR INTEGRATION OF BITCELLS IN A VOLATILE MEMORY ARRAY AND BITCELLS IN A NON-VOLATILE MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/833154 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833154 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833154
Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array Mar 26, 2020 Issued
Array ( [id] => 16585806 [patent_doc_number] => 20210020208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => APPARATUS AND METHOD FOR IMPROVING INPUT/OUTPUT THROUGHPUT OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/827225 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16827225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/827225
Apparatus and method for improving input/output throughput of memory system Mar 22, 2020 Issued
Array ( [id] => 16803099 [patent_doc_number] => 10998050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => High-voltage shifter with reduced transistor degradation [patent_app_type] => utility [patent_app_number] => 16/813273 [patent_app_country] => US [patent_app_date] => 2020-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 15641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813273 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813273
High-voltage shifter with reduced transistor degradation Mar 8, 2020 Issued
Array ( [id] => 16677045 [patent_doc_number] => 20210065811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => METHOD OF IMPROVING READ CURRENT STABILITY IN ANALOG NON-VOLATILE MEMORY BY LIMITING TIME GAP BETWEEN ERASE AND PROGRAM [patent_app_type] => utility [patent_app_number] => 16/803418 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3712 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803418 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/803418
Method of improving read current stability in analog non-volatile memory by limiting time gap between erase and program Feb 26, 2020 Issued
Array ( [id] => 17224774 [patent_doc_number] => 11177284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same [patent_app_type] => utility [patent_app_number] => 16/798643 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 72 [patent_no_of_words] => 28439 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/798643
Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same Feb 23, 2020 Issued
Array ( [id] => 16835316 [patent_doc_number] => 11011577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => One-time programmable memory using gate-all-around structures [patent_app_type] => utility [patent_app_number] => 16/799809 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 89 [patent_no_of_words] => 27672 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799809
One-time programmable memory using gate-all-around structures Feb 23, 2020 Issued
Array ( [id] => 16707467 [patent_doc_number] => 10957409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => Method of performing programming operation and related memory device [patent_app_type] => utility [patent_app_number] => 16/792304 [patent_app_country] => US [patent_app_date] => 2020-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16792304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/792304
Method of performing programming operation and related memory device Feb 16, 2020 Issued
Array ( [id] => 16020385 [patent_doc_number] => 20200185036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => MEMORY SYSTEM HAVING SEMICONDUCTOR MEMORY DEVICE THAT PERFORMS VERIFY OPERATIONS USING VARIOUS VERIFY VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/791607 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791607
Memory system having semiconductor memory device that performs verify operations using various verify voltages Feb 13, 2020 Issued
Array ( [id] => 16943955 [patent_doc_number] => 11056203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-06 [patent_title] => Boosted bitlines for storage cell programmed state verification in a memory array [patent_app_type] => utility [patent_app_number] => 16/788194 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 12941 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788194 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788194
Boosted bitlines for storage cell programmed state verification in a memory array Feb 10, 2020 Issued
Array ( [id] => 17137471 [patent_doc_number] => 11139036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-05 [patent_title] => Using variable voltages to discharge electrons from a memory array during verify recovery operations [patent_app_type] => utility [patent_app_number] => 16/786948 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6577 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786948
Using variable voltages to discharge electrons from a memory array during verify recovery operations Feb 9, 2020 Issued
Array ( [id] => 16707452 [patent_doc_number] => 10957394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-23 [patent_title] => NAND string pre-charge during programming by injecting holes via substrate [patent_app_type] => utility [patent_app_number] => 16/785973 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 15013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785973
NAND string pre-charge during programming by injecting holes via substrate Feb 9, 2020 Issued
Array ( [id] => 16787690 [patent_doc_number] => 10990119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Reference voltage generation circuit, power-on detection circuit, and semiconductor device for preventing internal circuit from operating incorrectly at low voltage [patent_app_type] => utility [patent_app_number] => 16/784663 [patent_app_country] => US [patent_app_date] => 2020-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16784663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/784663
Reference voltage generation circuit, power-on detection circuit, and semiconductor device for preventing internal circuit from operating incorrectly at low voltage Feb 6, 2020 Issued
Array ( [id] => 16707767 [patent_doc_number] => 10957711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Ferroelectric device with multiple polarization states and method of making the same [patent_app_type] => utility [patent_app_number] => 16/778245 [patent_app_country] => US [patent_app_date] => 2020-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 41 [patent_no_of_words] => 16093 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16778245 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/778245
Ferroelectric device with multiple polarization states and method of making the same Jan 30, 2020 Issued
Array ( [id] => 16845732 [patent_doc_number] => 11017825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Memory circuit including tracking circuit [patent_app_type] => utility [patent_app_number] => 16/777682 [patent_app_country] => US [patent_app_date] => 2020-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16777682 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/777682
Memory circuit including tracking circuit Jan 29, 2020 Issued
Array ( [id] => 15775231 [patent_doc_number] => 20200118633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/713091 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713091 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713091
Non-volatile semiconductor memory device in which erase and write operations are sequentially performed to control voltage thresholds of memory cells Dec 12, 2019 Issued
Array ( [id] => 16819656 [patent_doc_number] => 11004493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-11 [patent_title] => Differential amplifier sensing schemes for non-switching state compensation [patent_app_type] => utility [patent_app_number] => 16/705055 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 34421 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705055 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/705055
Differential amplifier sensing schemes for non-switching state compensation Dec 4, 2019 Issued
Array ( [id] => 17092674 [patent_doc_number] => 11120868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Semiconductor memory device using shared data line for read/write operation [patent_app_type] => utility [patent_app_number] => 16/703928 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703928
Semiconductor memory device using shared data line for read/write operation Dec 4, 2019 Issued
Array ( [id] => 17107230 [patent_doc_number] => 11127455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Fin-FET gain cells [patent_app_type] => utility [patent_app_number] => 16/699003 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8955 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699003 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/699003
Fin-FET gain cells Nov 27, 2019 Issued
Array ( [id] => 15597115 [patent_doc_number] => 20200075092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => MEMORY READ STABILITY ENHANCEMENT WITH SHORT SEGMENTED BIT LINE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/676850 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/676850
Memory read stability enhancement with short segmented bit line architecture Nov 6, 2019 Issued
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