
Reema Patel
Examiner (ID: 4332, Phone: (571)270-1436 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1405 |
| Issued Applications | 1166 |
| Pending Applications | 125 |
| Abandoned Applications | 157 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18945753
[patent_doc_number] => 20240040892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => DISPLAY PANEL AND TEMPERATURE REGULATION METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 17/623599
[patent_app_country] => US
[patent_app_date] => 2021-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4630
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623599
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/623599 | Display panel and temperature regulation method therefor | Dec 22, 2021 | Issued |
Array
(
[id] => 17752685
[patent_doc_number] => 20220230890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-21
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING GALLIUM OXIDE-BASED SEMICONDUCTOR LAYER
[patent_app_type] => utility
[patent_app_number] => 17/551274
[patent_app_country] => US
[patent_app_date] => 2021-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2370
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551274
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/551274 | Method for manufacturing semiconductor device having gallium oxide-based semiconductor layer | Dec 14, 2021 | Issued |
Array
(
[id] => 18608080
[patent_doc_number] => 11749558
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-05
[patent_title] => Treating a silicon on insulator wafer in preparation for manufacturing an atomistic electronic device interfaced with a CMOS electronic device
[patent_app_type] => utility
[patent_app_number] => 17/548782
[patent_app_country] => US
[patent_app_date] => 2021-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4745
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548782
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/548782 | Treating a silicon on insulator wafer in preparation for manufacturing an atomistic electronic device interfaced with a CMOS electronic device | Dec 12, 2021 | Issued |
Array
(
[id] => 20443206
[patent_doc_number] => 12514052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-30
[patent_title] => Light emitting element and display device including the same
[patent_app_type] => utility
[patent_app_number] => 17/522373
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 29648
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522373
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/522373 | Light emitting element and display device including the same | Nov 8, 2021 | Issued |
Array
(
[id] => 19428457
[patent_doc_number] => 12087895
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Image display device manufacturing method and image display device
[patent_app_type] => utility
[patent_app_number] => 17/522394
[patent_app_country] => US
[patent_app_date] => 2021-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 60
[patent_no_of_words] => 20217
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522394
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/522394 | Image display device manufacturing method and image display device | Nov 8, 2021 | Issued |
Array
(
[id] => 17612973
[patent_doc_number] => 20220155253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => BIOSENSORS WITH CHARGE SENSING AND DEBYE SCREENING
[patent_app_type] => utility
[patent_app_number] => 17/521647
[patent_app_country] => US
[patent_app_date] => 2021-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5167
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521647
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/521647 | BIOSENSORS WITH CHARGE SENSING AND DEBYE SCREENING | Nov 7, 2021 | Abandoned |
Array
(
[id] => 17431646
[patent_doc_number] => 20220059355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP IN PATTERN-DENSE REGION
[patent_app_type] => utility
[patent_app_number] => 17/516698
[patent_app_country] => US
[patent_app_date] => 2021-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8598
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -6
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516698
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/516698 | Method for preparing semiconductor device with air gap in pattern-dense region | Nov 1, 2021 | Issued |
Array
(
[id] => 18821426
[patent_doc_number] => 20230395767
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/032276
[patent_app_country] => US
[patent_app_date] => 2021-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7088
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18032276
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/032276 | DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE | Oct 18, 2021 | Pending |
Array
(
[id] => 19294562
[patent_doc_number] => 12033926
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Method of manufacturing semiconductor devices with a paddle and electrically conductive clip and corresponding semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/498328
[patent_app_country] => US
[patent_app_date] => 2021-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 3314
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498328
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/498328 | Method of manufacturing semiconductor devices with a paddle and electrically conductive clip and corresponding semiconductor device | Oct 10, 2021 | Issued |
Array
(
[id] => 18282476
[patent_doc_number] => 20230097948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => TRANSISTOR STRUCTURES WITH REDUCED SOURCE/DRAIN LEAKAGE THROUGH BACKSIDE TREATMENT OF SUBFIN SEMICONDUCTOR MATERIAL
[patent_app_type] => utility
[patent_app_number] => 17/485340
[patent_app_country] => US
[patent_app_date] => 2021-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9278
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485340
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485340 | TRANSISTOR STRUCTURES WITH REDUCED SOURCE/DRAIN LEAKAGE THROUGH BACKSIDE TREATMENT OF SUBFIN SEMICONDUCTOR MATERIAL | Sep 24, 2021 | Pending |
Array
(
[id] => 18286288
[patent_doc_number] => 20230101760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => STACKED 2D CMOS WITH INTER METAL LAYERS
[patent_app_type] => utility
[patent_app_number] => 17/485225
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5461
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485225
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/485225 | Stacked 2D CMOS with inter metal layers | Sep 23, 2021 | Issued |
Array
(
[id] => 18751501
[patent_doc_number] => 11810822
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-07
[patent_title] => Apparatuses and methods including patterns in scribe regions of semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 17/481489
[patent_app_country] => US
[patent_app_date] => 2021-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 9563
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481489
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/481489 | Apparatuses and methods including patterns in scribe regions of semiconductor devices | Sep 21, 2021 | Issued |
Array
(
[id] => 17949564
[patent_doc_number] => 20220336583
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/479454
[patent_app_country] => US
[patent_app_date] => 2021-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10902
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479454
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/479454 | Integrated circuit structure and method for forming the same | Sep 19, 2021 | Issued |
Array
(
[id] => 18757673
[patent_doc_number] => 20230361136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => PIXEL STRUCTURE AND METHOD FOR MANUFACTURING A PIXEL STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/246398
[patent_app_country] => US
[patent_app_date] => 2021-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4110
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246398
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/246398 | PIXEL STRUCTURE AND METHOD FOR MANUFACTURING A PIXEL STRUCTURE | Sep 14, 2021 | Abandoned |
Array
(
[id] => 18252059
[patent_doc_number] => 20230079098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-16
[patent_title] => FIELD EFFECT TRANSISTORS WITH GATE FINS AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/474699
[patent_app_country] => US
[patent_app_date] => 2021-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19719
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474699
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/474699 | Field effect transistors with gate fins and method of making the same | Sep 13, 2021 | Issued |
Array
(
[id] => 17318990
[patent_doc_number] => 20210408040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => VERTICAL SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/473006
[patent_app_country] => US
[patent_app_date] => 2021-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10224
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473006
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/473006 | Vertical semiconductor devices | Sep 12, 2021 | Issued |
Array
(
[id] => 20509094
[patent_doc_number] => 12543386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-03
[patent_title] => Image sensor including unit pixels
[patent_app_type] => utility
[patent_app_number] => 17/471537
[patent_app_country] => US
[patent_app_date] => 2021-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 10229
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471537
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/471537 | Image sensor including unit pixels | Sep 9, 2021 | Issued |
Array
(
[id] => 19494387
[patent_doc_number] => 12113111
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Semiconductor structure including gate structure including barrier layer and conductive layer and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/470090
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4552
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470090
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/470090 | Semiconductor structure including gate structure including barrier layer and conductive layer and manufacturing method thereof | Sep 8, 2021 | Issued |
Array
(
[id] => 19705168
[patent_doc_number] => 12199216
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-14
[patent_title] => Display device featuring spaced apart insulating layer patterns
[patent_app_type] => utility
[patent_app_number] => 17/470383
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 15604
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470383
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/470383 | Display device featuring spaced apart insulating layer patterns | Sep 8, 2021 | Issued |
Array
(
[id] => 20390734
[patent_doc_number] => 12490482
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-02
[patent_title] => Semiconductor device having improved p-type doped nitride-based semiconductor layer and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/598893
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 2097
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17598893
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/598893 | Semiconductor device having improved p-type doped nitride-based semiconductor layer and method for manufacturing the same | Sep 6, 2021 | Issued |