Search

Reema Patel

Examiner (ID: 4332, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1405
Issued Applications
1166
Pending Applications
125
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18190797 [patent_doc_number] => 11581401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Pin diode including a conductive layer, and fabrication process [patent_app_type] => utility [patent_app_number] => 17/370397 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370397
Pin diode including a conductive layer, and fabrication process Jul 7, 2021 Issued
Array ( [id] => 17339375 [patent_doc_number] => 20220005706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES [patent_app_type] => utility [patent_app_number] => 17/305192 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305192
Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities Jun 30, 2021 Issued
Array ( [id] => 19428152 [patent_doc_number] => 12087585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Low-temperature implant for buried layer formation [patent_app_type] => utility [patent_app_number] => 17/362946 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2662 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362946 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362946
Low-temperature implant for buried layer formation Jun 28, 2021 Issued
Array ( [id] => 19364276 [patent_doc_number] => 20240266310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/569607 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18569607 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/569607
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Jun 22, 2021 Pending
Array ( [id] => 18081103 [patent_doc_number] => 20220406715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => STACKED FET INTEGRATION WITH BSPDN [patent_app_type] => utility [patent_app_number] => 17/304460 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17304460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/304460
Stacked FET integration with BSPDN Jun 21, 2021 Issued
Array ( [id] => 17145381 [patent_doc_number] => 20210313394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/353521 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353521
Semiconductor structure and manufacturing method of the same Jun 20, 2021 Issued
Array ( [id] => 17145312 [patent_doc_number] => 20210313325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => METAL GATE MODULATION TO IMPROVE KINK EFFECT [patent_app_type] => utility [patent_app_number] => 17/351392 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351392 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351392
Metal gate modulation to improve kink effect Jun 17, 2021 Issued
Array ( [id] => 17583243 [patent_doc_number] => 20220140098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => Nano Transistors with Source/Drain Having Side Contacts to 2-D Material [patent_app_type] => utility [patent_app_number] => 17/351622 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351622
Nano transistors with source/drain having side contacts to 2-D material Jun 17, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 18190825 [patent_doc_number] => 11581429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Power semiconductor switch having a cross-trench structure [patent_app_type] => utility [patent_app_number] => 17/350505 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16473 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350505 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350505
Power semiconductor switch having a cross-trench structure Jun 16, 2021 Issued
Array ( [id] => 19935120 [patent_doc_number] => 12308328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Semiconductor memory device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/345184 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 1299 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345184
Semiconductor memory device and method for manufacturing the same Jun 10, 2021 Issued
Array ( [id] => 18654644 [patent_doc_number] => 20230300492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => METHOD FOR MANUFACTURING LIGHT DETECTION DEVICE, LIGHT DETECTION DEVICE, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/999845 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/999845
Method for manufacturing light detection device, light detection device, and electronic device Jun 2, 2021 Issued
Array ( [id] => 17933511 [patent_doc_number] => 20220328637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => Process and Structure for Source/Drain Contacts [patent_app_type] => utility [patent_app_number] => 17/338384 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338384
Process and structure for source/drain contacts Jun 2, 2021 Issued
Array ( [id] => 18040382 [patent_doc_number] => 20220384599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => NANOSTRUCTURED CHANNEL REGIONS FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/334541 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334541 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334541
Nanostructured channel regions for semiconductor devices May 27, 2021 Issued
Array ( [id] => 19271635 [patent_doc_number] => 20240215342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => DISPLAY DEVICE, AND DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/915522 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17915522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/915522
DISPLAY DEVICE, AND DISPLAY PANEL AND MANUFACTURING METHOD THEREOF May 27, 2021 Pending
Array ( [id] => 17100123 [patent_doc_number] => 20210287914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => ETCHING PROCESS WITH IN-SITU FORMATION OF PROTECTIVE LAYER [patent_app_type] => utility [patent_app_number] => 17/334326 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17334326 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/334326
Etching process with in-situ formation of protective layer May 27, 2021 Issued
Array ( [id] => 17085681 [patent_doc_number] => 20210280688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => NANOSHEET TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/328674 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6777 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328674
Nanosheet transistor May 23, 2021 Issued
Array ( [id] => 17660793 [patent_doc_number] => 20220181258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => POWER-TAP PASS-THROUGH TO CONNECT A BURIED POWER RAIL TO FRONT-SIDE POWER DISTRIBUTION NETWORK [patent_app_type] => utility [patent_app_number] => 17/328236 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328236
Power-tap pass-through to connect a buried power rail to front-side power distribution network May 23, 2021 Issued
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