Search

Reema Patel

Examiner (ID: 6667, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1385
Issued Applications
1154
Pending Applications
133
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18222134 [patent_doc_number] => 20230061128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/464479 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464479
MEMORY DEVICE AND METHOD OF FABRICATING THE SAME Aug 31, 2021 Abandoned
Array ( [id] => 18182934 [patent_doc_number] => 20230043664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => BACKSIDE ILLUMINATED IMAGE SENSOR AND MANUFACTURING METHOD THEREFORE [patent_app_type] => utility [patent_app_number] => 17/458586 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5175 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458586
Backside illuminated image sensor and manufacturing method therefore Aug 26, 2021 Issued
Array ( [id] => 18680058 [patent_doc_number] => 20230317716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/024296 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18024296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/024296
SEMICONDUCTOR DEVICE Aug 25, 2021 Issued
Array ( [id] => 19079601 [patent_doc_number] => 11948981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Seam-filling of metal gates with Si-containing layers [patent_app_type] => utility [patent_app_number] => 17/405406 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 44 [patent_no_of_words] => 7970 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405406
Seam-filling of metal gates with Si-containing layers Aug 17, 2021 Issued
Array ( [id] => 17416990 [patent_doc_number] => 20220051894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME [patent_app_type] => utility [patent_app_number] => 17/403265 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/403265
CRYSTALLINE TRANSITION METAL DICHALCOGENIDE FILMS AND METHODS OF MAKING SAME Aug 15, 2021 Abandoned
Array ( [id] => 17933544 [patent_doc_number] => 20220328670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => CHANNEL STRUCTURES INCLUDING DOPED 2D MATERIALS FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/400076 [patent_app_country] => US [patent_app_date] => 2021-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400076 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400076
Channel structures including doped 2D materials for semiconductor devices Aug 10, 2021 Issued
Array ( [id] => 17217788 [patent_doc_number] => 20210351126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => INTEGRATED FAN-OUT PACKAGES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/382371 [patent_app_country] => US [patent_app_date] => 2021-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/382371
Integrated fan-out packages and methods of forming the same Jul 21, 2021 Issued
Array ( [id] => 17217905 [patent_doc_number] => 20210351243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => DISPLAY DEVICES, DISPLAY PANELS AND TRANSPARENT DISPLAY PANELS THEREOF [patent_app_type] => utility [patent_app_number] => 17/381569 [patent_app_country] => US [patent_app_date] => 2021-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381569
Display devices, display panels and transparent display panels thereof Jul 20, 2021 Issued
Array ( [id] => 20334531 [patent_doc_number] => 12464827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Resistor with exponential-weighted trim [patent_app_type] => utility [patent_app_number] => 17/376747 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376747
Resistor with exponential-weighted trim Jul 14, 2021 Issued
Array ( [id] => 20334531 [patent_doc_number] => 12464827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Resistor with exponential-weighted trim [patent_app_type] => utility [patent_app_number] => 17/376747 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/376747
Resistor with exponential-weighted trim Jul 14, 2021 Issued
Array ( [id] => 20390738 [patent_doc_number] => 12490486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Compound semiconductor substrate and method for manufacturing compound semiconductor substrate [patent_app_type] => utility [patent_app_number] => 18/016177 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 9830 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18016177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/016177
Compound semiconductor substrate and method for manufacturing compound semiconductor substrate Jul 12, 2021 Issued
Array ( [id] => 20390738 [patent_doc_number] => 12490486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Compound semiconductor substrate and method for manufacturing compound semiconductor substrate [patent_app_type] => utility [patent_app_number] => 18/016177 [patent_app_country] => US [patent_app_date] => 2021-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 9830 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18016177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/016177
Compound semiconductor substrate and method for manufacturing compound semiconductor substrate Jul 12, 2021 Issued
Array ( [id] => 20332771 [patent_doc_number] => 12463055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Package substrate manufacturing method [patent_app_type] => utility [patent_app_number] => 18/005608 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/005608
Package substrate manufacturing method Jul 8, 2021 Issued
Array ( [id] => 20332771 [patent_doc_number] => 12463055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Package substrate manufacturing method [patent_app_type] => utility [patent_app_number] => 18/005608 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18005608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/005608
Package substrate manufacturing method Jul 8, 2021 Issued
Array ( [id] => 19294691 [patent_doc_number] => 12034056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Semiconductor devices including gate structures with gate spacers [patent_app_type] => utility [patent_app_number] => 17/371907 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/371907
Semiconductor devices including gate structures with gate spacers Jul 8, 2021 Issued
Array ( [id] => 18190797 [patent_doc_number] => 11581401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Pin diode including a conductive layer, and fabrication process [patent_app_type] => utility [patent_app_number] => 17/370397 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370397
Pin diode including a conductive layer, and fabrication process Jul 7, 2021 Issued
Array ( [id] => 18357901 [patent_doc_number] => 11646308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Through silicon via design for stacking integrated circuits [patent_app_type] => utility [patent_app_number] => 17/370045 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370045 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370045
Through silicon via design for stacking integrated circuits Jul 7, 2021 Issued
Array ( [id] => 18124133 [patent_doc_number] => 20230009745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SEMICONDUCTOR DEVICE, AND METHOD FOR PROTECTING LOW-K DIELECTRIC FEATURE OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/370265 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370265 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370265
Semiconductor device, and method for protecting low-k dielectric feature of semiconductor device Jul 7, 2021 Issued
Array ( [id] => 17339375 [patent_doc_number] => 20220005706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => METHOD FOR MAKING A SEMICONDUCTOR DEVICE USING SUPERLATTICES WITH DIFFERENT NON-SEMICONDUCTOR THERMAL STABILITIES [patent_app_type] => utility [patent_app_number] => 17/305192 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17305192 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/305192
Method for making a semiconductor superlattices with different non-semiconductor thermal stabilities Jun 30, 2021 Issued
Array ( [id] => 19428152 [patent_doc_number] => 12087585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Low-temperature implant for buried layer formation [patent_app_type] => utility [patent_app_number] => 17/362946 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2662 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362946 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362946
Low-temperature implant for buried layer formation Jun 28, 2021 Issued
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