Search

Reema Patel

Examiner (ID: 12235, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1436
Issued Applications
1190
Pending Applications
119
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17676604 [patent_doc_number] => 20220189771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => UNDERLAYER FILM FOR SEMICONDUCTOR DEVICE FORMATION [patent_app_type] => utility [patent_app_number] => 17/157548 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157548
UNDERLAYER FILM FOR SEMICONDUCTOR DEVICE FORMATION Jan 24, 2021 Abandoned
Array ( [id] => 17130271 [patent_doc_number] => 20210305040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => PHOTORESIST LAYER SURFACE TREATMENT, CAP LAYER, AND METHOD OF FORMING PHOTORESIST PATTERN [patent_app_type] => utility [patent_app_number] => 17/150403 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150403
Photoresist layer surface treatment, cap layer, and method of forming photoresist pattern Jan 14, 2021 Issued
Array ( [id] => 17925912 [patent_doc_number] => 11469175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Semiconductor device with programmable unit and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/149032 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9787 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149032 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149032
Semiconductor device with programmable unit and method for fabricating the same Jan 13, 2021 Issued
Array ( [id] => 16812271 [patent_doc_number] => 20210134826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => HYBRID BONDING CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/148209 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148209 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148209
Hybrid bonding contact structure of three-dimensional memory device Jan 12, 2021 Issued
Array ( [id] => 17645211 [patent_doc_number] => 20220172950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Method of Manipulating Deposition Ratges of Poly-Silicon and Method of Manufacturing a SiGe HBT Device [patent_app_type] => utility [patent_app_number] => 17/145070 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145070 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145070
Method of manipulating deposition rates of poly-silicon and method of manufacturing a SiGe HBT device Jan 7, 2021 Issued
Array ( [id] => 17668379 [patent_doc_number] => 11362084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-14 [patent_title] => ESD protection [patent_app_type] => utility [patent_app_number] => 17/143703 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143703
ESD protection Jan 6, 2021 Issued
Array ( [id] => 16936431 [patent_doc_number] => 20210202320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => Local Gate Height Tuning by Cmp And Dummy Gate Design [patent_app_type] => utility [patent_app_number] => 17/125299 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125299 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125299
Local gate height tuning by CMP and dummy gate design Dec 16, 2020 Issued
Array ( [id] => 17630622 [patent_doc_number] => 20220165637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => THERMAL SUBSTRATE CONTACT [patent_app_type] => utility [patent_app_number] => 17/122749 [patent_app_country] => US [patent_app_date] => 2020-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11381 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17122749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/122749
Thermal substrate contact Dec 14, 2020 Issued
Array ( [id] => 18277013 [patent_doc_number] => 11615960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Method for removing re-sputtered material from patterned sidewalls [patent_app_type] => utility [patent_app_number] => 17/110194 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 41 [patent_no_of_words] => 3602 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110194
Method for removing re-sputtered material from patterned sidewalls Dec 1, 2020 Issued
Array ( [id] => 16715882 [patent_doc_number] => 20210083029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => METHOD FOR MANUFACTURING A DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/109369 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109369
Method for manufacturing a display device Dec 1, 2020 Issued
Array ( [id] => 16765658 [patent_doc_number] => 20210111240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => DISPLAY DEVICE INCLUDING A FLEXIBLE SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/108586 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108586
Display device including a flexible substrate Nov 30, 2020 Issued
Array ( [id] => 17926056 [patent_doc_number] => 11469320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => High voltage semiconductor device having bootstrap diode [patent_app_type] => utility [patent_app_number] => 17/107185 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9232 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107185
High voltage semiconductor device having bootstrap diode Nov 29, 2020 Issued
Array ( [id] => 18131289 [patent_doc_number] => 11557506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Methods for processing a semiconductor substrate [patent_app_type] => utility [patent_app_number] => 17/104559 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104559 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104559
Methods for processing a semiconductor substrate Nov 24, 2020 Issued
Array ( [id] => 16752540 [patent_doc_number] => 20210104552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 17/104563 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104563 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104563
Semiconductor integrated circuit device Nov 24, 2020 Issued
Array ( [id] => 18131449 [patent_doc_number] => 11557666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => High electron mobility transistor and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 17/100935 [patent_app_country] => US [patent_app_date] => 2020-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3111 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100935
High electron mobility transistor and fabrication method thereof Nov 21, 2020 Issued
Array ( [id] => 18000991 [patent_doc_number] => 11502102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Three-dimensional memory devices and fabrication methods thereof [patent_app_type] => utility [patent_app_number] => 17/100871 [patent_app_country] => US [patent_app_date] => 2020-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 59 [patent_no_of_words] => 16916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100871
Three-dimensional memory devices and fabrication methods thereof Nov 20, 2020 Issued
Array ( [id] => 17908702 [patent_doc_number] => 11462565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Three-dimensional memory devices and fabrication methods thereof [patent_app_type] => utility [patent_app_number] => 17/100869 [patent_app_country] => US [patent_app_date] => 2020-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 59 [patent_no_of_words] => 17993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100869
Three-dimensional memory devices and fabrication methods thereof Nov 20, 2020 Issued
Array ( [id] => 16858569 [patent_doc_number] => 20210159314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SINGLE CRYSTAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/100340 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17100340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/100340
Single crystal semiconductor structure and method of fabricating the same Nov 19, 2020 Issued
Array ( [id] => 17956418 [patent_doc_number] => 11482532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Joint opening structures of three-dimensional memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/951141 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 120 [patent_figures_cnt] => 132 [patent_no_of_words] => 26947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951141 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951141
Joint opening structures of three-dimensional memory devices and methods for forming the same Nov 17, 2020 Issued
Array ( [id] => 18235932 [patent_doc_number] => 11600496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => In-situ p-type activation of III-nitride films grown via metal organic chemical vapor deposition [patent_app_type] => utility [patent_app_number] => 16/951376 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951376
In-situ p-type activation of III-nitride films grown via metal organic chemical vapor deposition Nov 17, 2020 Issued
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