
Reema Patel
Examiner (ID: 12235, Phone: (571)270-1436 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1436 |
| Issued Applications | 1190 |
| Pending Applications | 119 |
| Abandoned Applications | 157 |
Applications
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|---|---|---|---|
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