Search

Reema Patel

Examiner (ID: 12235, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1436
Issued Applications
1190
Pending Applications
119
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16677735 [patent_doc_number] => 20210066501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/098046 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098046
Semiconductor device Nov 12, 2020 Issued
Array ( [id] => 18175304 [patent_doc_number] => 11575023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Secure chip identification using random threshold voltage variation in a field effect transistor structure as a physically unclonable function [patent_app_type] => utility [patent_app_number] => 17/094848 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5750 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094848 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094848
Secure chip identification using random threshold voltage variation in a field effect transistor structure as a physically unclonable function Nov 10, 2020 Issued
Array ( [id] => 17607322 [patent_doc_number] => 11335814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Semiconductor chip [patent_app_type] => utility [patent_app_number] => 17/095593 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4929 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095593
Semiconductor chip Nov 10, 2020 Issued
Array ( [id] => 17574429 [patent_doc_number] => 11322704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Organic light-emitting diode, organic light-emitting display including the same, and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/093291 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093291 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093291
Organic light-emitting diode, organic light-emitting display including the same, and method of manufacturing the same Nov 8, 2020 Issued
Array ( [id] => 17500656 [patent_doc_number] => 11289366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Method of manufacturing semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/089681 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 4921 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/089681
Method of manufacturing semiconductor structure Nov 3, 2020 Issued
Array ( [id] => 16631796 [patent_doc_number] => 20210050449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/087218 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087218
Semiconductor device with fin and related methods Nov 1, 2020 Issued
Array ( [id] => 19161054 [patent_doc_number] => 20240153761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SUBSTRATE STRIPPING METHOD AND EPITAXIAL WAFER [patent_app_type] => utility [patent_app_number] => 17/773293 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17773293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/773293
Substrate stripping method and epitaxial wafer Oct 29, 2020 Issued
Array ( [id] => 17566521 [patent_doc_number] => 20220130670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => STRAIN RELIEF TRENCHES FOR EPITAXIAL GROWTH [patent_app_type] => utility [patent_app_number] => 16/949373 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16949373 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/949373
Strain relief trenches for epitaxial growth Oct 26, 2020 Issued
Array ( [id] => 17700136 [patent_doc_number] => 11373869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Semiconductor device and fabrication method [patent_app_type] => utility [patent_app_number] => 17/079545 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8272 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079545
Semiconductor device and fabrication method Oct 25, 2020 Issued
Array ( [id] => 16617250 [patent_doc_number] => 20210035903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/074474 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074474
Semiconductor structure and manufacturing method thereof Oct 18, 2020 Issued
Array ( [id] => 16936368 [patent_doc_number] => 20210202257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => PLASMA-BASED EDGE TERMINATIONS FOR GALLIUM NITRIDE POWER DEVICES [patent_app_type] => utility [patent_app_number] => 17/072622 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072622 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072622
Plasma-based edge terminations for gallium nitride power devices Oct 15, 2020 Issued
Array ( [id] => 17818712 [patent_doc_number] => 11424336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Gate contact over active region in cell [patent_app_type] => utility [patent_app_number] => 17/070335 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070335
Gate contact over active region in cell Oct 13, 2020 Issued
Array ( [id] => 17536653 [patent_doc_number] => 20220115262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => BULK WAFER SWITCH ISOLATION [patent_app_type] => utility [patent_app_number] => 17/069098 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069098
Bulk wafer switch isolation Oct 12, 2020 Issued
Array ( [id] => 16765439 [patent_doc_number] => 20210111021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/068785 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068785
Method of forming a semiconductor device structure Oct 11, 2020 Issued
Array ( [id] => 17536772 [patent_doc_number] => 20220115381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING FIN STRUCTURES AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/066923 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066923
Semiconductor structure having fin structures and method of manufacturing the same Oct 8, 2020 Issued
Array ( [id] => 19444639 [patent_doc_number] => 12094931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Semiconductor device and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/037768 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7321 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037768 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037768
Semiconductor device and method for manufacturing the same Sep 29, 2020 Issued
Array ( [id] => 17898746 [patent_doc_number] => 20220308408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/418441 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17418441 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/418441
Array substrate, method for manufacturing the same and display device Sep 29, 2020 Issued
Array ( [id] => 17395797 [patent_doc_number] => 11244821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Method for preparing isolation area of gallium oxide device [patent_app_type] => utility [patent_app_number] => 17/036126 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2671 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036126
Method for preparing isolation area of gallium oxide device Sep 28, 2020 Issued
Array ( [id] => 16692343 [patent_doc_number] => 20210074822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SONOS STACK WITH SPLIT NITRIDE MEMORY LAYER [patent_app_type] => utility [patent_app_number] => 17/035129 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035129 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035129
Sonos stack with split nitride memory layer Sep 27, 2020 Issued
Array ( [id] => 17107400 [patent_doc_number] => 11127626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Method of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/033759 [patent_app_country] => US [patent_app_date] => 2020-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5342 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033759
Method of manufacturing a semiconductor device Sep 25, 2020 Issued
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