
Reema Patel
Examiner (ID: 6667, Phone: (571)270-1436 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1385 |
| Issued Applications | 1154 |
| Pending Applications | 133 |
| Abandoned Applications | 157 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17518550
[patent_doc_number] => 11297727
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-05
[patent_title] => Power electronic module
[patent_app_type] => utility
[patent_app_number] => 16/598131
[patent_app_country] => US
[patent_app_date] => 2019-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2050
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598131
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/598131 | Power electronic module | Oct 9, 2019 | Issued |
Array
(
[id] => 16536782
[patent_doc_number] => 10879397
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 16/595875
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 5877
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16595875
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/595875 | Semiconductor structure | Oct 7, 2019 | Issued |
Array
(
[id] => 17536681
[patent_doc_number] => 20220115290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => SEMICONDUCTOR COMPONENT ARRANGEMENT, METHOD FOR FABRICATION THEREOF AND HEAT DISSIPATION DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/285295
[patent_app_country] => US
[patent_app_date] => 2019-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7199
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17285295
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/285295 | Semiconductor component arrangement, method for fabrication thereof and heat dissipation device | Oct 7, 2019 | Issued |
Array
(
[id] => 16789190
[patent_doc_number] => 10991629
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Method of forming protection layer in FinFET device
[patent_app_type] => utility
[patent_app_number] => 16/583052
[patent_app_country] => US
[patent_app_date] => 2019-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 5813
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583052
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/583052 | Method of forming protection layer in FinFET device | Sep 24, 2019 | Issued |
Array
(
[id] => 15718181
[patent_doc_number] => 20200105858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-02
[patent_title] => DISPLAY APPRATUS AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/580042
[patent_app_country] => US
[patent_app_date] => 2019-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9183
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580042
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/580042 | Display apparatus and method of manufacturing the same | Sep 23, 2019 | Issued |
Array
(
[id] => 17032852
[patent_doc_number] => 11094670
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-17
[patent_title] => Semiconductor device assemblies including multiple shingled stacks of semiconductor dies
[patent_app_type] => utility
[patent_app_number] => 16/578592
[patent_app_country] => US
[patent_app_date] => 2019-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4047
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578592
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/578592 | Semiconductor device assemblies including multiple shingled stacks of semiconductor dies | Sep 22, 2019 | Issued |
Array
(
[id] => 16739026
[patent_doc_number] => 10964692
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Through silicon via design for stacking integrated circuits
[patent_app_type] => utility
[patent_app_number] => 16/578299
[patent_app_country] => US
[patent_app_date] => 2019-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 7774
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 223
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578299
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/578299 | Through silicon via design for stacking integrated circuits | Sep 20, 2019 | Issued |
Array
(
[id] => 15351773
[patent_doc_number] => 20200013778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => METAL GATE MODULATION TO IMPROVE KINK EFFECT
[patent_app_type] => utility
[patent_app_number] => 16/574205
[patent_app_country] => US
[patent_app_date] => 2019-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11224
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574205
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/574205 | Metal gate modulation to improve kink effect | Sep 17, 2019 | Issued |
Array
(
[id] => 17949215
[patent_doc_number] => 20220336234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => METHOD OF FABRICATING A LATTICE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/753820
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17753820
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/753820 | METHOD OF FABRICATING A LATTICE STRUCTURE | Sep 15, 2019 | Abandoned |
Array
(
[id] => 15299841
[patent_doc_number] => 20190393056
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-26
[patent_title] => SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIUM
[patent_app_type] => utility
[patent_app_number] => 16/563466
[patent_app_country] => US
[patent_app_date] => 2019-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11053
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563466
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/563466 | Substrate processing apparatus, method of manufacturing semiconductor device, and recording medium | Sep 5, 2019 | Issued |
Array
(
[id] => 16402401
[patent_doc_number] => 20200343259
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-29
[patent_title] => VERTICAL SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/562919
[patent_app_country] => US
[patent_app_date] => 2019-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10209
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562919
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/562919 | Vertical semiconductor devices | Sep 5, 2019 | Issued |
Array
(
[id] => 16080849
[patent_doc_number] => 20200194411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => PHOTOCOUPLER AND PACKAGING MEMBER THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/562886
[patent_app_country] => US
[patent_app_date] => 2019-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5832
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 412
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562886
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/562886 | Photocoupler and packaging member thereof | Sep 5, 2019 | Issued |
Array
(
[id] => 16692272
[patent_doc_number] => 20210074751
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => IMAGE SENSOR WITH REDUCED PETAL FLARE
[patent_app_type] => utility
[patent_app_number] => 16/563052
[patent_app_country] => US
[patent_app_date] => 2019-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3884
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563052
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/563052 | Image sensor with reduced petal flare | Sep 5, 2019 | Issued |
Array
(
[id] => 16645526
[patent_doc_number] => 10923392
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-16
[patent_title] => Interconnect structure and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 16/562207
[patent_app_country] => US
[patent_app_date] => 2019-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 9476
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562207
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/562207 | Interconnect structure and method of forming the same | Sep 4, 2019 | Issued |
Array
(
[id] => 15332523
[patent_doc_number] => 20200006591
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-02
[patent_title] => CONDUCTIVE ISOLATION BETWEEN PHOTOTRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 16/558957
[patent_app_country] => US
[patent_app_date] => 2019-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558957
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/558957 | Conductive isolation between phototransistors | Sep 2, 2019 | Issued |
Array
(
[id] => 17787716
[patent_doc_number] => 11410850
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-09
[patent_title] => Aluminum oxide semiconductor manufacturing method and aluminum oxide semiconductor manufacturing device
[patent_app_type] => utility
[patent_app_number] => 17/272869
[patent_app_country] => US
[patent_app_date] => 2019-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 15807
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17272869
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/272869 | Aluminum oxide semiconductor manufacturing method and aluminum oxide semiconductor manufacturing device | Aug 29, 2019 | Issued |
Array
(
[id] => 16495899
[patent_doc_number] => 10861951
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Transistor layout to reduce kink effect
[patent_app_type] => utility
[patent_app_number] => 16/550497
[patent_app_country] => US
[patent_app_date] => 2019-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 25
[patent_no_of_words] => 8288
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550497
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/550497 | Transistor layout to reduce kink effect | Aug 25, 2019 | Issued |
Array
(
[id] => 15260117
[patent_doc_number] => 20190378792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-12
[patent_title] => SWITCHING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/549376
[patent_app_country] => US
[patent_app_date] => 2019-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3412
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549376
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/549376 | Switching device | Aug 22, 2019 | Issued |
Array
(
[id] => 15598077
[patent_doc_number] => 20200075573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-03-05
[patent_title] => RESISTOR WITH EXPONENTIAL-WEIGHTED TRIM
[patent_app_type] => utility
[patent_app_number] => 16/547615
[patent_app_country] => US
[patent_app_date] => 2019-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5157
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547615
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/547615 | Resistor with exponential-weighted trim | Aug 21, 2019 | Issued |
Array
(
[id] => 17032963
[patent_doc_number] => 11094783
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-17
[patent_title] => Semiconductor device having a silicon oxide film with a gradual downward inclination and method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/547628
[patent_app_country] => US
[patent_app_date] => 2019-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 39
[patent_no_of_words] => 7750
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547628
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/547628 | Semiconductor device having a silicon oxide film with a gradual downward inclination and method of manufacturing semiconductor device | Aug 21, 2019 | Issued |