Search

Reema Patel

Examiner (ID: 12235, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1436
Issued Applications
1190
Pending Applications
119
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11932748 [patent_doc_number] => 09799752 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-24 [patent_title] => 'Method for forming a thin-film transistor' [patent_app_type] => utility [patent_app_number] => 15/338576 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 63 [patent_no_of_words] => 13058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338576 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338576
Method for forming a thin-film transistor Oct 30, 2016 Issued
Array ( [id] => 11673716 [patent_doc_number] => 20170162439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/338775 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2791 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338775 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338775
Method of manufacturing semiconductor device Oct 30, 2016 Issued
Array ( [id] => 11673716 [patent_doc_number] => 20170162439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/338775 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2791 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338775 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338775
Method of manufacturing semiconductor device Oct 30, 2016 Issued
Array ( [id] => 11898239 [patent_doc_number] => 09768180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Methods and apparatus for three-dimensional nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 15/338372 [patent_app_country] => US [patent_app_date] => 2016-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 42 [patent_no_of_words] => 12013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15338372 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/338372
Methods and apparatus for three-dimensional nonvolatile memory Oct 28, 2016 Issued
Array ( [id] => 13159697 [patent_doc_number] => 10096584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Method for producing a power semiconductor module [patent_app_type] => utility [patent_app_number] => 15/337733 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4386 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15337733 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/337733
Method for producing a power semiconductor module Oct 27, 2016 Issued
Array ( [id] => 11446208 [patent_doc_number] => 20170047229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF' [patent_app_type] => utility [patent_app_number] => 15/334307 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5652 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/334307
Stack frame for electrical connections and the method to fabricate thereof Oct 25, 2016 Issued
Array ( [id] => 13099035 [patent_doc_number] => 10068863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-04 [patent_title] => Formation of solder and copper interconnect structures and associated techniques and configurations [patent_app_type] => utility [patent_app_number] => 15/293103 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 11239 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15293103 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/293103
Formation of solder and copper interconnect structures and associated techniques and configurations Oct 12, 2016 Issued
Array ( [id] => 13019521 [patent_doc_number] => 10032880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Method for forming ohmic contacts [patent_app_type] => utility [patent_app_number] => 15/289519 [patent_app_country] => US [patent_app_date] => 2016-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 3466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289519 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/289519
Method for forming ohmic contacts Oct 9, 2016 Issued
Array ( [id] => 12195485 [patent_doc_number] => 09899220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Method for patterning a substrate involving directed self-assembly' [patent_app_type] => utility [patent_app_number] => 15/289550 [patent_app_country] => US [patent_app_date] => 2016-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 43 [patent_no_of_words] => 4902 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/289550
Method for patterning a substrate involving directed self-assembly Oct 9, 2016 Issued
Array ( [id] => 11608264 [patent_doc_number] => 20170125568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/289534 [patent_app_country] => US [patent_app_date] => 2016-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8935 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289534 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/289534
Compound semiconductor device and method of manufacturing the same Oct 9, 2016 Issued
Array ( [id] => 11623037 [patent_doc_number] => 20170133224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'INTEGRATED PROCESS AND STRUCTURE TO FORM III-V CHANNEL FOR SUB-7NM CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 15/277394 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277394 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277394
Integrated process and structure to form III-V channel for sub-7nm CMOS devices Sep 26, 2016 Issued
Array ( [id] => 12061984 [patent_doc_number] => 20170338328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'METHOD OF FORMING INTERNAL DIELECTRIC SPACERS FOR HORIZONTAL NANOSHEET FET ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 15/276784 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6155 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276784 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/276784
Method of forming internal dielectric spacers for horizontal nanosheet FET architectures Sep 25, 2016 Issued
Array ( [id] => 11898123 [patent_doc_number] => 09768062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Method for forming low parasitic capacitance source and drain contacts' [patent_app_type] => utility [patent_app_number] => 15/276748 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276748 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/276748
Method for forming low parasitic capacitance source and drain contacts Sep 25, 2016 Issued
Array ( [id] => 11623040 [patent_doc_number] => 20170133227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/276722 [patent_app_country] => US [patent_app_date] => 2016-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8239 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15276722 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/276722
Method of manufacturing semiconductor device Sep 25, 2016 Issued
Array ( [id] => 11386071 [patent_doc_number] => 20170012127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-12 [patent_title] => 'SEMICONDUCTOR DEVICE WITH FIN AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 15/255862 [patent_app_country] => US [patent_app_date] => 2016-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3915 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15255862 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/255862
Semiconductor device with fin and related methods Sep 1, 2016 Issued
Array ( [id] => 15110517 [patent_doc_number] => 10476598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-12 [patent_title] => Optical communication circuits [patent_app_type] => utility [patent_app_number] => 15/219005 [patent_app_country] => US [patent_app_date] => 2016-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4341 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15219005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/219005
Optical communication circuits Jul 24, 2016 Issued
Array ( [id] => 11539579 [patent_doc_number] => 09613996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Backside structure and methods for BSI image sensors' [patent_app_type] => utility [patent_app_number] => 15/218266 [patent_app_country] => US [patent_app_date] => 2016-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15218266 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/218266
Backside structure and methods for BSI image sensors Jul 24, 2016 Issued
Array ( [id] => 11353885 [patent_doc_number] => 20160372625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'ADVANCED HYDROGENATION OF SILICON SOLAR CELLS' [patent_app_type] => utility [patent_app_number] => 15/204813 [patent_app_country] => US [patent_app_date] => 2016-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 20619 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15204813 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/204813
Advanced hydrogenation of silicon solar cells Jul 6, 2016 Issued
Array ( [id] => 12195856 [patent_doc_number] => 09899595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Implementing deposition growth method for magnetic memory' [patent_app_type] => utility [patent_app_number] => 15/197847 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 52 [patent_no_of_words] => 6403 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15197847 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/197847
Implementing deposition growth method for magnetic memory Jun 29, 2016 Issued
Array ( [id] => 11110907 [patent_doc_number] => 20160307877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 15/193875 [patent_app_country] => US [patent_app_date] => 2016-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14134 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193875 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/193875
Semiconductor device and manufacturing method of the same Jun 26, 2016 Issued
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