Search

Reema Patel

Examiner (ID: 4332, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1405
Issued Applications
1166
Pending Applications
125
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20416794 [patent_doc_number] => 12500087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Semiconductor structure with air gap in pattern-dense region and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/220963 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 7007 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18220963 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/220963
Semiconductor structure with air gap in pattern-dense region and method of manufacturing the same Jul 11, 2023 Issued
Array ( [id] => 19733923 [patent_doc_number] => 12211925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Gate-all-around integrated circuit structures having oxide sub-fins [patent_app_type] => utility [patent_app_number] => 18/219986 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 14148 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219986
Gate-all-around integrated circuit structures having oxide sub-fins Jul 9, 2023 Issued
Array ( [id] => 18745653 [patent_doc_number] => 20230354647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/347778 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4068 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347778
Display device Jul 5, 2023 Issued
Array ( [id] => 19057051 [patent_doc_number] => 20240099020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/345266 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345266
MEMORY DEVICE Jun 29, 2023 Pending
Array ( [id] => 19662055 [patent_doc_number] => 20240429120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => Topside Cooling for Semiconductor Device [patent_app_type] => utility [patent_app_number] => 18/340503 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340503 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340503
Topside Cooling for Semiconductor Device Jun 22, 2023 Pending
Array ( [id] => 19646477 [patent_doc_number] => 20240420997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SELECTIVE LINER DEPOSITION FOR VIA RESISTANCE REDUCTION [patent_app_type] => utility [patent_app_number] => 18/211502 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211502 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211502
SELECTIVE LINER DEPOSITION FOR VIA RESISTANCE REDUCTION Jun 18, 2023 Pending
Array ( [id] => 19275787 [patent_doc_number] => 12025914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Silver patterning and interconnect processes [patent_app_type] => utility [patent_app_number] => 18/327785 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6250 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327785 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327785
Silver patterning and interconnect processes May 31, 2023 Issued
Array ( [id] => 18696318 [patent_doc_number] => 20230326754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => PHOTORESIST LAYER SURFACE TREATMENT, CAP LAYER, AND METHOD OF FORMING PHOTORESIST PATTERN [patent_app_type] => utility [patent_app_number] => 18/204259 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18204259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/204259
Photoresist layer surface treatment, cap layer, and method of forming photoresist pattern May 30, 2023 Issued
Array ( [id] => 18653119 [patent_doc_number] => 20230298959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => HIGH-FREQUENCY MODULE AND COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/324314 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324314 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324314
High-frequency module and communication device May 25, 2023 Issued
Array ( [id] => 19589862 [patent_doc_number] => 20240387419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => DIRECT HYBRID BOND PAD HAVING TAPERED SIDEWALL [patent_app_type] => utility [patent_app_number] => 18/319786 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319786
DIRECT HYBRID BOND PAD HAVING TAPERED SIDEWALL May 17, 2023 Pending
Array ( [id] => 19590161 [patent_doc_number] => 20240387718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => HETEROJUNCTION STRUCTURE WITH VARYING LAYER COMPOSITION [patent_app_type] => utility [patent_app_number] => 18/320063 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320063 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320063
HETEROJUNCTION STRUCTURE WITH VARYING LAYER COMPOSITION May 17, 2023 Pending
Array ( [id] => 18883042 [patent_doc_number] => 20240006411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/318587 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9156 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318587
SEMICONDUCTOR DEVICE May 15, 2023 Pending
Array ( [id] => 19146444 [patent_doc_number] => 20240145474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/314484 [patent_app_country] => US [patent_app_date] => 2023-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18314484 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/314484
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME May 8, 2023 Pending
Array ( [id] => 18791240 [patent_doc_number] => 20230380246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => ELECTROLUMINESCENCE DISPLAY [patent_app_type] => utility [patent_app_number] => 18/144648 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18144648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/144648
ELECTROLUMINESCENCE DISPLAY May 7, 2023 Pending
Array ( [id] => 20244166 [patent_doc_number] => 12424497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Method for transferring a layer from a source substrate to a destination substrate [patent_app_type] => utility [patent_app_number] => 18/865498 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18865498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/865498
Method for transferring a layer from a source substrate to a destination substrate May 3, 2023 Issued
Array ( [id] => 19559917 [patent_doc_number] => 20240371709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 18/311220 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311220
SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME May 1, 2023 Pending
Array ( [id] => 19559936 [patent_doc_number] => 20240371728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS [patent_app_type] => utility [patent_app_number] => 18/141552 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141552 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141552
BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS Apr 30, 2023 Pending
Array ( [id] => 19531921 [patent_doc_number] => 20240355823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/306101 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18306101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/306101
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME Apr 23, 2023 Pending
Array ( [id] => 20583126 [patent_doc_number] => 12575389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Method for fabricating semiconductor structures [patent_app_type] => utility [patent_app_number] => 18/547151 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 46 [patent_no_of_words] => 2150 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18547151 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/547151
Method for fabricating semiconductor structures Apr 19, 2023 Issued
Array ( [id] => 18555289 [patent_doc_number] => 20230253306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/303557 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7431 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303557 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303557
Semiconductor structure and manufacturing method thereof Apr 18, 2023 Issued
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