
Reema Patel
Examiner (ID: 12235, Phone: (571)270-1436 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812 |
| Total Applications | 1436 |
| Issued Applications | 1190 |
| Pending Applications | 119 |
| Abandoned Applications | 157 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19823385
[patent_doc_number] => 20250081592
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => CONTACT RESISTANCE REDUCTION FOR DIRECT BACKSIDE CONTACT
[patent_app_type] => utility
[patent_app_number] => 18/242943
[patent_app_country] => US
[patent_app_date] => 2023-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3693
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242943
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/242943 | CONTACT RESISTANCE REDUCTION FOR DIRECT BACKSIDE CONTACT | Sep 5, 2023 | Pending |
Array
(
[id] => 19531798
[patent_doc_number] => 20240355700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-24
[patent_title] => DIE-PACKAGE INTERCONNECT TO FACILITATE THERMAL CONDUCTION
[patent_app_type] => utility
[patent_app_number] => 18/458367
[patent_app_country] => US
[patent_app_date] => 2023-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10369
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458367
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458367 | DIE-PACKAGE INTERCONNECT TO FACILITATE THERMAL CONDUCTION | Aug 29, 2023 | Pending |
Array
(
[id] => 19812521
[patent_doc_number] => 12243934
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-04
[patent_title] => Channel structures including doped 2D materials for semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 18/452581
[patent_app_country] => US
[patent_app_date] => 2023-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 77
[patent_no_of_words] => 15205
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452581
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/452581 | Channel structures including doped 2D materials for semiconductor devices | Aug 20, 2023 | Issued |
Array
(
[id] => 18821263
[patent_doc_number] => 20230395604
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-07
[patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/234678
[patent_app_country] => US
[patent_app_date] => 2023-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8229
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 255
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234678
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/234678 | Semiconductor integrated circuit device | Aug 15, 2023 | Issued |
Array
(
[id] => 19943581
[patent_doc_number] => 12315717
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Method for manufacturing metal oxynitride film
[patent_app_type] => utility
[patent_app_number] => 18/232881
[patent_app_country] => US
[patent_app_date] => 2023-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 57
[patent_no_of_words] => 12461
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232881
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/232881 | Method for manufacturing metal oxynitride film | Aug 10, 2023 | Issued |
Array
(
[id] => 19007702
[patent_doc_number] => 20240071773
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => ION IMPLANTATION FOR INCREASED ADHESION WITH RESIST MATERIAL
[patent_app_type] => utility
[patent_app_number] => 18/232916
[patent_app_country] => US
[patent_app_date] => 2023-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7336
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232916
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/232916 | ION IMPLANTATION FOR INCREASED ADHESION WITH RESIST MATERIAL | Aug 10, 2023 | Pending |
Array
(
[id] => 19567763
[patent_doc_number] => 12142542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-12
[patent_title] => Semiconductor device having a thermal contact and method of making
[patent_app_type] => utility
[patent_app_number] => 18/447927
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 11593
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447927
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447927 | Semiconductor device having a thermal contact and method of making | Aug 9, 2023 | Issued |
Array
(
[id] => 19654600
[patent_doc_number] => 12176401
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Seam-filling of metal gates with Si-containing layers
[patent_app_type] => utility
[patent_app_number] => 18/446681
[patent_app_country] => US
[patent_app_date] => 2023-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 44
[patent_no_of_words] => 7991
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446681
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/446681 | Seam-filling of metal gates with Si-containing layers | Aug 8, 2023 | Issued |
Array
(
[id] => 19926435
[patent_doc_number] => 12300731
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Multigate device with air gap spacer and backside rail contact and method of fabricating thereof
[patent_app_type] => utility
[patent_app_number] => 18/446151
[patent_app_country] => US
[patent_app_date] => 2023-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 53
[patent_no_of_words] => 9122
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446151
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/446151 | Multigate device with air gap spacer and backside rail contact and method of fabricating thereof | Aug 7, 2023 | Issued |
Array
(
[id] => 19773433
[patent_doc_number] => 20250054859
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/231453
[patent_app_country] => US
[patent_app_date] => 2023-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4583
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231453
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/231453 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME | Aug 7, 2023 | Pending |
Array
(
[id] => 19733916
[patent_doc_number] => 12211918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Nanostructured channel regions for semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 18/231486
[patent_app_country] => US
[patent_app_date] => 2023-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 68
[patent_figures_cnt] => 68
[patent_no_of_words] => 9063
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231486
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/231486 | Nanostructured channel regions for semiconductor devices | Aug 7, 2023 | Issued |
Array
(
[id] => 18789656
[patent_doc_number] => 20230378365
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => MULTI-GATE DEVICE AND RELATED METHODS
[patent_app_type] => utility
[patent_app_number] => 18/366392
[patent_app_country] => US
[patent_app_date] => 2023-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14669
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366392
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/366392 | Multi-gate device and related methods | Aug 6, 2023 | Issued |
Array
(
[id] => 19639706
[patent_doc_number] => 12170323
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-17
[patent_title] => Nano transistors with source/drain having side contacts to 2-D material
[patent_app_type] => utility
[patent_app_number] => 18/365995
[patent_app_country] => US
[patent_app_date] => 2023-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 33
[patent_no_of_words] => 7228
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365995
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/365995 | Nano transistors with source/drain having side contacts to 2-D material | Aug 5, 2023 | Issued |
Array
(
[id] => 18789548
[patent_doc_number] => 20230378234
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => IMAGE SENSOR DEVICE AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/365680
[patent_app_country] => US
[patent_app_date] => 2023-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365680
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/365680 | Image sensor device and methods of forming the same | Aug 3, 2023 | Issued |
Array
(
[id] => 18789297
[patent_doc_number] => 20230377948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => METHOD FOR FORMING A SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/365402
[patent_app_country] => US
[patent_app_date] => 2023-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10000
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365402
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/365402 | Method for forming a semiconductor-on-insulator (SOI) substrate | Aug 3, 2023 | Issued |
Array
(
[id] => 18812590
[patent_doc_number] => 20230386927
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => Local Gate Height Tuning by CMP and Dummy Gate Design
[patent_app_type] => utility
[patent_app_number] => 18/365405
[patent_app_country] => US
[patent_app_date] => 2023-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10914
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365405
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/365405 | Local gate height tuning by CMP and dummy gate design | Aug 3, 2023 | Issued |
Array
(
[id] => 19720345
[patent_doc_number] => 12205888
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Semiconductor packages and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 18/363692
[patent_app_country] => US
[patent_app_date] => 2023-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 5611
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363692
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/363692 | Semiconductor packages and methods of forming the same | Jul 31, 2023 | Issued |
Array
(
[id] => 20675439
[patent_doc_number] => 12615973
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-28
[patent_title] => Strain relief trenches for epitaxial growth
[patent_app_type] => utility
[patent_app_number] => 18/362240
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 2115
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362240
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362240 | Strain relief trenches for epitaxial growth | Jul 30, 2023 | Issued |
Array
(
[id] => 19926431
[patent_doc_number] => 12300727
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-13
[patent_title] => Process and structure for source/drain contacts
[patent_app_type] => utility
[patent_app_number] => 18/361262
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 32
[patent_no_of_words] => 3270
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361262
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361262 | Process and structure for source/drain contacts | Jul 27, 2023 | Issued |
Array
(
[id] => 19751675
[patent_doc_number] => 20250040240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-30
[patent_title] => STACKED FIELD EFFECT TRANSISTOR HYBRID GATE CUT
[patent_app_type] => utility
[patent_app_number] => 18/361255
[patent_app_country] => US
[patent_app_date] => 2023-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10456
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361255
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/361255 | STACKED FIELD EFFECT TRANSISTOR HYBRID GATE CUT | Jul 27, 2023 | Pending |