Search

Reema Patel

Examiner (ID: 12235, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1436
Issued Applications
1190
Pending Applications
119
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8944014 [patent_doc_number] => 08497192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Method of manufacturing a semiconductor device and substrate processing apparatus' [patent_app_type] => utility [patent_app_number] => 13/178232 [patent_app_country] => US [patent_app_date] => 2011-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 12714 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178232 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178232
Method of manufacturing a semiconductor device and substrate processing apparatus Jul 6, 2011 Issued
Array ( [id] => 9482993 [patent_doc_number] => 08728944 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Method of removing contaminants and native oxides from a substrate surface' [patent_app_type] => utility [patent_app_number] => 13/177409 [patent_app_country] => US [patent_app_date] => 2011-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13177409 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/177409
Method of removing contaminants and native oxides from a substrate surface Jul 5, 2011 Issued
Array ( [id] => 8221389 [patent_doc_number] => 20120135594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'METHOD FOR FORMING A GATE ELECTRODE' [patent_app_type] => utility [patent_app_number] => 13/177517 [patent_app_country] => US [patent_app_date] => 2011-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4092 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13177517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/177517
Method for forming a gate electrode Jul 5, 2011 Issued
Array ( [id] => 7720384 [patent_doc_number] => 20120009719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'IMAGE SENSORS INCLUDING HYDROPHOBIC INTERFACES AND METHODS OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/177358 [patent_app_country] => US [patent_app_date] => 2011-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11669 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20120009719.pdf [firstpage_image] =>[orig_patent_app_number] => 13177358 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/177358
Image sensors including hydrophobic interfaces and methods of fabricating the same Jul 5, 2011 Issued
Array ( [id] => 8871173 [patent_doc_number] => 08466552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-18 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/165689 [patent_app_country] => US [patent_app_date] => 2011-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 5099 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13165689 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/165689
Semiconductor device and method of manufacturing the same Jun 20, 2011 Issued
Array ( [id] => 8760011 [patent_doc_number] => 08420531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Enhanced diffusion barrier for interconnect structures' [patent_app_type] => utility [patent_app_number] => 13/164929 [patent_app_country] => US [patent_app_date] => 2011-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 5998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13164929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/164929
Enhanced diffusion barrier for interconnect structures Jun 20, 2011 Issued
Array ( [id] => 8519850 [patent_doc_number] => 20120319258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/163770 [patent_app_country] => US [patent_app_date] => 2011-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4824 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163770 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/163770
Stack frame for electrical connections and the method to fabricate thereof Jun 19, 2011 Issued
Array ( [id] => 8571618 [patent_doc_number] => 08338263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Etching narrow, tall dielectric isolation structures from a dielectric layer' [patent_app_type] => utility [patent_app_number] => 13/164619 [patent_app_country] => US [patent_app_date] => 2011-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 6809 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13164619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/164619
Etching narrow, tall dielectric isolation structures from a dielectric layer Jun 19, 2011 Issued
Array ( [id] => 9239099 [patent_doc_number] => 08603890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Air gap isolation in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/162475 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 89 [patent_no_of_words] => 17185 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162475 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162475
Air gap isolation in non-volatile memory Jun 15, 2011 Issued
Array ( [id] => 8513771 [patent_doc_number] => 20120313178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING METAL GATE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/158479 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8081 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13158479 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/158479
Semiconductor device having metal gate and manufacturing method thereof Jun 12, 2011 Issued
Array ( [id] => 8821604 [patent_doc_number] => 20130122649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'METHOD FOR MANUFACTURING THIN FILM TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/376833 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3965 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13376833 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/376833
METHOD FOR MANUFACTURING THIN FILM TRANSISTOR Jun 12, 2011 Abandoned
Array ( [id] => 8726065 [patent_doc_number] => 08405187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Chip package with channel stiffener frame' [patent_app_type] => utility [patent_app_number] => 13/158048 [patent_app_country] => US [patent_app_date] => 2011-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13158048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/158048
Chip package with channel stiffener frame Jun 9, 2011 Issued
Array ( [id] => 8513759 [patent_doc_number] => 20120313167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING GRADIENT DOPING PROFILE' [patent_app_type] => utility [patent_app_number] => 13/157930 [patent_app_country] => US [patent_app_date] => 2011-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4840 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13157930 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/157930
Semiconductor device having gradient doping profile Jun 9, 2011 Issued
Array ( [id] => 7480912 [patent_doc_number] => 20110233720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'TREATMENT FOR BONDING INTERFACE STABILIZATION' [patent_app_type] => utility [patent_app_number] => 13/153709 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6176 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20110233720.pdf [firstpage_image] =>[orig_patent_app_number] => 13153709 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153709
Treatment for bonding interface stabilization Jun 5, 2011 Issued
Array ( [id] => 9254572 [patent_doc_number] => 08617988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Through-substrate vias' [patent_app_type] => utility [patent_app_number] => 13/154051 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5869 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13154051 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154051
Through-substrate vias Jun 5, 2011 Issued
Array ( [id] => 9183831 [patent_doc_number] => 08623763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Protective layer for protecting TSV tips during thermo-compressive bonding' [patent_app_type] => utility [patent_app_number] => 13/150899 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3523 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13150899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/150899
Protective layer for protecting TSV tips during thermo-compressive bonding May 31, 2011 Issued
Array ( [id] => 7648809 [patent_doc_number] => 20110298078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'METHOD FOR PRODUCTION OF SOLID-STATE IMAGING ELEMENT, SOLID-STATE IMAGING ELEMENT, AND IMAGING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/116539 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10530 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20110298078.pdf [firstpage_image] =>[orig_patent_app_number] => 13116539 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/116539
Method for production of solid-state imaging element, solid-state imaging element, and imaging apparatus May 25, 2011 Issued
Array ( [id] => 8689875 [patent_doc_number] => 08389402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Method for via formation in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/116432 [patent_app_country] => US [patent_app_date] => 2011-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2368 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13116432 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/116432
Method for via formation in a semiconductor device May 25, 2011 Issued
Array ( [id] => 8202817 [patent_doc_number] => 08188520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Field effect transistor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/104537 [patent_app_country] => US [patent_app_date] => 2011-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4893 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/188/08188520.pdf [firstpage_image] =>[orig_patent_app_number] => 13104537 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/104537
Field effect transistor and method for fabricating the same May 9, 2011 Issued
Array ( [id] => 9273912 [patent_doc_number] => 08637844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Method for fabrication of crystalline diodes for resistive memories' [patent_app_type] => utility [patent_app_number] => 13/097307 [patent_app_country] => US [patent_app_date] => 2011-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5743 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13097307 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/097307
Method for fabrication of crystalline diodes for resistive memories Apr 28, 2011 Issued
Menu