Search

Reema Patel

Examiner (ID: 4332, Phone: (571)270-1436 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
1405
Issued Applications
1166
Pending Applications
125
Abandoned Applications
157

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18266226 [patent_doc_number] => 20230087468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => HYBRID BONDING CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/052459 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052459
Hybrid bonding contact structure of three-dimensional memory device Nov 2, 2022 Issued
Array ( [id] => 18631865 [patent_doc_number] => 20230290770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => ESD PROTECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/052158 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18052158 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/052158
ESD protection circuit Nov 1, 2022 Issued
Array ( [id] => 18555519 [patent_doc_number] => 20230253536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/978323 [patent_app_country] => US [patent_app_date] => 2022-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17978323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/978323
DISPLAY DEVICE Oct 31, 2022 Pending
Array ( [id] => 18423913 [patent_doc_number] => 20230178377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/978048 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17978048 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/978048
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Oct 30, 2022 Pending
Array ( [id] => 20566072 [patent_doc_number] => 12568697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Image sensor [patent_app_type] => utility [patent_app_number] => 18/049851 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 10190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/049851
Image sensor Oct 25, 2022 Issued
Array ( [id] => 20376813 [patent_doc_number] => 12484269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/970608 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/970608
Semiconductor structure Oct 20, 2022 Issued
Array ( [id] => 18199167 [patent_doc_number] => 20230052686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SINGLE CRYSTAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/969420 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/969420
Single crystal semiconductor structure and method of fabricating the same Oct 18, 2022 Issued
Array ( [id] => 19376581 [patent_doc_number] => 12068161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-20 [patent_title] => Method for implant and anneal for high voltage field effect transistors [patent_app_type] => utility [patent_app_number] => 18/045071 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3179 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 433 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18045071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/045071
Method for implant and anneal for high voltage field effect transistors Oct 6, 2022 Issued
Array ( [id] => 19086115 [patent_doc_number] => 20240112916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => METAL GATE CUT FORMED AFTER SOURCE AND DRAIN CONTACTS [patent_app_type] => utility [patent_app_number] => 17/936934 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936934 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936934
METAL GATE CUT FORMED AFTER SOURCE AND DRAIN CONTACTS Sep 29, 2022 Pending
Array ( [id] => 20318071 [patent_doc_number] => 12456626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Etching method and plasma processing apparatus [patent_app_type] => utility [patent_app_number] => 17/955540 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/955540
Etching method and plasma processing apparatus Sep 28, 2022 Issued
Array ( [id] => 20246105 [patent_doc_number] => 12426451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Display apparatus including a shielding conductive layer [patent_app_type] => utility [patent_app_number] => 17/950227 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950227
Display apparatus including a shielding conductive layer Sep 21, 2022 Issued
Array ( [id] => 19095470 [patent_doc_number] => 11956953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Joint opening structures of three-dimensional memory devices and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/934161 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 120 [patent_figures_cnt] => 133 [patent_no_of_words] => 26970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934161
Joint opening structures of three-dimensional memory devices and methods for forming the same Sep 20, 2022 Issued
Array ( [id] => 18146414 [patent_doc_number] => 20230020271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/949241 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949241
High electron mobility transistor and fabrication method thereof Sep 20, 2022 Issued
Array ( [id] => 18140021 [patent_doc_number] => 20230013859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/947227 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947227 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/947227
Semiconductor structure and method for preparing semiconductor structure Sep 18, 2022 Issued
Array ( [id] => 20258990 [patent_doc_number] => 12431353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Hardmask structure and method of forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/946355 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7161 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946355
Hardmask structure and method of forming semiconductor structure Sep 15, 2022 Issued
Array ( [id] => 19054917 [patent_doc_number] => 20240096886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => HETEROGENEOUS GATE ALL AROUND DIELECTRIC THICKNESS [patent_app_type] => utility [patent_app_number] => 17/932557 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932557
Heterogeneous gate all around dielectric thickness Sep 14, 2022 Issued
Array ( [id] => 19055009 [patent_doc_number] => 20240096978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) APPARATUS WITH SELF-ALIGNED BACKSIDE CONTACT [patent_app_type] => utility [patent_app_number] => 17/946017 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946017
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) APPARATUS WITH SELF-ALIGNED BACKSIDE CONTACT Sep 14, 2022 Pending
Array ( [id] => 20319341 [patent_doc_number] => 12457905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features [patent_app_type] => utility [patent_app_number] => 17/943974 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943974
Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features Sep 12, 2022 Issued
Array ( [id] => 19038325 [patent_doc_number] => 20240088140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => HEIGHT CONTROL IN NANOSHEET DEVICES [patent_app_type] => utility [patent_app_number] => 17/943751 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943751
HEIGHT CONTROL IN NANOSHEET DEVICES Sep 12, 2022 Pending
Array ( [id] => 20132231 [patent_doc_number] => 12374549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Method of forming semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/901525 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901525
Method of forming semiconductor structure Aug 31, 2022 Issued
Menu