
Regan J. Rundio
Examiner (ID: 17498, Phone: (571)272-0685 , Office: P/2899 )
| Most Active Art Unit | 2899 |
| Art Unit(s) | 2899, 2812 |
| Total Applications | 251 |
| Issued Applications | 187 |
| Pending Applications | 0 |
| Abandoned Applications | 64 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9148466
[patent_doc_number] => 20130302989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-14
[patent_title] => 'REDUCING LINE EDGE ROUGHNESS IN HARDMASK INTEGRATION SCHEMES'
[patent_app_type] => utility
[patent_app_number] => 13/466215
[patent_app_country] => US
[patent_app_date] => 2012-05-08
[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466215
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/466215 | REDUCING LINE EDGE ROUGHNESS IN HARDMASK INTEGRATION SCHEMES | May 7, 2012 | Abandoned |
Array
(
[id] => 9662208
[patent_doc_number] => 08809184
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-19
[patent_title] => 'Methods of forming contacts for semiconductor devices using a local interconnect processing scheme'
[patent_app_type] => utility
[patent_app_number] => 13/465633
[patent_app_country] => US
[patent_app_date] => 2012-05-07
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/465633 | Methods of forming contacts for semiconductor devices using a local interconnect processing scheme | May 6, 2012 | Issued |
Array
(
[id] => 9132094
[patent_doc_number] => 20130292807
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'Semiconductor Device Dielectric Interface Layer'
[patent_app_type] => utility
[patent_app_number] => 13/465340
[patent_app_country] => US
[patent_app_date] => 2012-05-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/465340 | Semiconductor device dielectric interface layer | May 6, 2012 | Issued |
Array
(
[id] => 8489584
[patent_doc_number] => 20120288991
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-15
[patent_title] => 'BURNTHROUGH FORMULATIONS'
[patent_app_type] => utility
[patent_app_number] => 13/465244
[patent_app_country] => US
[patent_app_date] => 2012-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/465244 | Burnthrough formulations | May 6, 2012 | Issued |
Array
(
[id] => 9503450
[patent_doc_number] => 08741763
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[patent_kind] => B2
[patent_issue_date] => 2014-06-03
[patent_title] => 'Layout designs with via routing structures'
[patent_app_type] => utility
[patent_app_number] => 13/465129
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/465129 | Layout designs with via routing structures | May 6, 2012 | Issued |
Array
(
[id] => 9074266
[patent_doc_number] => 08551843
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-10-08
[patent_title] => 'Methods of forming CMOS semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 13/465486
[patent_app_country] => US
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Array
(
[id] => 9131934
[patent_doc_number] => 20130292647
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'METHODS OF FORMING HYDROPHOBIC SURFACES ON SEMICONDUCTOR DEVICE STRUCTURES, METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND SEMICONDUCTOR DEVICE STRUCTURES'
[patent_app_type] => utility
[patent_app_number] => 13/464645
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[patent_effective_date] => 0000-00-00
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464645
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/464645 | Methods of forming hydrophobic surfaces on semiconductor device structures, methods of forming semiconductor device structures, and semiconductor device structures | May 3, 2012 | Issued |
Array
(
[id] => 9299730
[patent_doc_number] => 08647957
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[patent_kind] => B2
[patent_issue_date] => 2014-02-11
[patent_title] => 'Method for making semi-conductor nanocrystals'
[patent_app_type] => utility
[patent_app_number] => 13/464363
[patent_app_country] => US
[patent_app_date] => 2012-05-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/464363 | Method for making semi-conductor nanocrystals | May 3, 2012 | Issued |
Array
(
[id] => 10035561
[patent_doc_number] => 09076887
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[patent_kind] => B2
[patent_issue_date] => 2015-07-07
[patent_title] => 'Method of fabricating a vertical diffusion metal-oxide-semiconductor transistor'
[patent_app_type] => utility
[patent_app_number] => 13/464584
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Array
(
[id] => 10028628
[patent_doc_number] => 09070534
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[patent_issue_date] => 2015-06-30
[patent_title] => 'Ion beam dimension control for ion implantation process and apparatus, and advanced process control'
[patent_app_type] => utility
[patent_app_number] => 13/463942
[patent_app_country] => US
[patent_app_date] => 2012-05-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/463942 | Ion beam dimension control for ion implantation process and apparatus, and advanced process control | May 3, 2012 | Issued |
Array
(
[id] => 9413511
[patent_doc_number] => 08697548
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[patent_title] => 'Method for making semi-conductor nanocrystals oriented along a predefined direction'
[patent_app_type] => utility
[patent_app_number] => 13/464390
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/464390 | Method for making semi-conductor nanocrystals oriented along a predefined direction | May 3, 2012 | Issued |
Array
(
[id] => 9135021
[patent_doc_number] => 20130295736
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'FABRICATION METHOD OF TRENCH POWER SEMICONDUCTOR STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 13/464913
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/464913 | FABRICATION METHOD OF TRENCH POWER SEMICONDUCTOR STRUCTURE | May 3, 2012 | Abandoned |
Array
(
[id] => 9995752
[patent_doc_number] => 09040346
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[patent_title] => 'Semiconductor package and methods of formation thereof'
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Array
(
[id] => 9135023
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[patent_title] => 'SEMICONDUCTOR PROCESS'
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Array
(
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Array
(
[id] => 9091356
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[patent_title] => 'Metal Grid in Backside Illumination Image Sensor Chips and Methods for Forming the Same'
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Array
(
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[patent_title] => 'METHODS OF FORMING VARYING DEPTH TRENCHES IN SEMICONDUCTOR DEVICES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/402674 | Methods of forming varying depth trenches in semiconductor devices | Feb 21, 2012 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/398059 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF | Feb 15, 2012 | Abandoned |