Search

Regan J. Rundio

Examiner (ID: 17498, Phone: (571)272-0685 , Office: P/2899 )

Most Active Art Unit
2899
Art Unit(s)
2899, 2812
Total Applications
251
Issued Applications
187
Pending Applications
0
Abandoned Applications
64

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9148466 [patent_doc_number] => 20130302989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'REDUCING LINE EDGE ROUGHNESS IN HARDMASK INTEGRATION SCHEMES' [patent_app_type] => utility [patent_app_number] => 13/466215 [patent_app_country] => US [patent_app_date] => 2012-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9627 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13466215 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/466215
REDUCING LINE EDGE ROUGHNESS IN HARDMASK INTEGRATION SCHEMES May 7, 2012 Abandoned
Array ( [id] => 9662208 [patent_doc_number] => 08809184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Methods of forming contacts for semiconductor devices using a local interconnect processing scheme' [patent_app_type] => utility [patent_app_number] => 13/465633 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 5202 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465633
Methods of forming contacts for semiconductor devices using a local interconnect processing scheme May 6, 2012 Issued
Array ( [id] => 9132094 [patent_doc_number] => 20130292807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'Semiconductor Device Dielectric Interface Layer' [patent_app_type] => utility [patent_app_number] => 13/465340 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465340
Semiconductor device dielectric interface layer May 6, 2012 Issued
Array ( [id] => 8489584 [patent_doc_number] => 20120288991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'BURNTHROUGH FORMULATIONS' [patent_app_type] => utility [patent_app_number] => 13/465244 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3427 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465244 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465244
Burnthrough formulations May 6, 2012 Issued
Array ( [id] => 9503450 [patent_doc_number] => 08741763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Layout designs with via routing structures' [patent_app_type] => utility [patent_app_number] => 13/465129 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3061 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465129 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465129
Layout designs with via routing structures May 6, 2012 Issued
Array ( [id] => 9074266 [patent_doc_number] => 08551843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-08 [patent_title] => 'Methods of forming CMOS semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/465486 [patent_app_country] => US [patent_app_date] => 2012-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5147 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/465486
Methods of forming CMOS semiconductor devices May 6, 2012 Issued
Array ( [id] => 9131934 [patent_doc_number] => 20130292647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'METHODS OF FORMING HYDROPHOBIC SURFACES ON SEMICONDUCTOR DEVICE STRUCTURES, METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND SEMICONDUCTOR DEVICE STRUCTURES' [patent_app_type] => utility [patent_app_number] => 13/464645 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8932 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464645 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464645
Methods of forming hydrophobic surfaces on semiconductor device structures, methods of forming semiconductor device structures, and semiconductor device structures May 3, 2012 Issued
Array ( [id] => 9299730 [patent_doc_number] => 08647957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Method for making semi-conductor nanocrystals' [patent_app_type] => utility [patent_app_number] => 13/464363 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6415 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464363 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464363
Method for making semi-conductor nanocrystals May 3, 2012 Issued
Array ( [id] => 10035561 [patent_doc_number] => 09076887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-07 [patent_title] => 'Method of fabricating a vertical diffusion metal-oxide-semiconductor transistor' [patent_app_type] => utility [patent_app_number] => 13/464584 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3907 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464584 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464584
Method of fabricating a vertical diffusion metal-oxide-semiconductor transistor May 3, 2012 Issued
Array ( [id] => 10028628 [patent_doc_number] => 09070534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Ion beam dimension control for ion implantation process and apparatus, and advanced process control' [patent_app_type] => utility [patent_app_number] => 13/463942 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5327 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463942
Ion beam dimension control for ion implantation process and apparatus, and advanced process control May 3, 2012 Issued
Array ( [id] => 9413511 [patent_doc_number] => 08697548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Method for making semi-conductor nanocrystals oriented along a predefined direction' [patent_app_type] => utility [patent_app_number] => 13/464390 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4343 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464390 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464390
Method for making semi-conductor nanocrystals oriented along a predefined direction May 3, 2012 Issued
Array ( [id] => 9135021 [patent_doc_number] => 20130295736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'FABRICATION METHOD OF TRENCH POWER SEMICONDUCTOR STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/464913 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2668 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464913
FABRICATION METHOD OF TRENCH POWER SEMICONDUCTOR STRUCTURE May 3, 2012 Abandoned
Array ( [id] => 9995752 [patent_doc_number] => 09040346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Semiconductor package and methods of formation thereof' [patent_app_type] => utility [patent_app_number] => 13/463636 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463636 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463636
Semiconductor package and methods of formation thereof May 2, 2012 Issued
Array ( [id] => 9135023 [patent_doc_number] => 20130295738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SEMICONDUCTOR PROCESS' [patent_app_type] => utility [patent_app_number] => 13/463809 [patent_app_country] => US [patent_app_date] => 2012-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3984 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463809 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463809
Semiconductor process May 2, 2012 Issued
Array ( [id] => 10151681 [patent_doc_number] => 09183977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Method for fabricating a coil by way of a rounded trench' [patent_app_type] => utility [patent_app_number] => 13/452669 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 6699 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452669 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452669
Method for fabricating a coil by way of a rounded trench Apr 19, 2012 Issued
Array ( [id] => 9091356 [patent_doc_number] => 20130270667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'Metal Grid in Backside Illumination Image Sensor Chips and Methods for Forming the Same' [patent_app_type] => utility [patent_app_number] => 13/449019 [patent_app_country] => US [patent_app_date] => 2012-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3007 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13449019 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/449019
Metal grid in backside illumination image sensor chips and methods for forming the same Apr 16, 2012 Issued
Array ( [id] => 8989892 [patent_doc_number] => 20130217173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'METHODS OF FORMING VARYING DEPTH TRENCHES IN SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 13/402674 [patent_app_country] => US [patent_app_date] => 2012-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13402674 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/402674
Methods of forming varying depth trenches in semiconductor devices Feb 21, 2012 Issued
Array ( [id] => 8370712 [patent_doc_number] => 20120220105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/397837 [patent_app_country] => US [patent_app_date] => 2012-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13397837 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/397837
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE Feb 15, 2012 Abandoned
Array ( [id] => 10001746 [patent_doc_number] => 09045825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Method of forming metal-containing film' [patent_app_type] => utility [patent_app_number] => 13/398523 [patent_app_country] => US [patent_app_date] => 2012-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 17468 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13398523 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/398523
Method of forming metal-containing film Feb 15, 2012 Issued
Array ( [id] => 8987138 [patent_doc_number] => 20130214419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/398059 [patent_app_country] => US [patent_app_date] => 2012-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1178 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13398059 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/398059
SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF Feb 15, 2012 Abandoned
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