Search

Regina M. Yoo

Examiner (ID: 17161, Phone: (571)272-6690 , Office: P/1799 )

Most Active Art Unit
1799
Art Unit(s)
1799, 1797, 1775, 1773, 1758, 1744
Total Applications
1121
Issued Applications
605
Pending Applications
113
Abandoned Applications
433

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6656045 [patent_doc_number] => 20030132521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method for electrical interconnection employing salicide bridge' [patent_app_type] => new [patent_app_number] => 10/292772 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5284 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20030132521.pdf [firstpage_image] =>[orig_patent_app_number] => 10292772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292772
Method for electrical interconnection employing salicide bridge Nov 11, 2002 Issued
Array ( [id] => 1264325 [patent_doc_number] => 06660568 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'BiLevel metallization for embedded back end of the line structures' [patent_app_type] => B1 [patent_app_number] => 10/290412 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1591 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660568.pdf [firstpage_image] =>[orig_patent_app_number] => 10290412 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290412
BiLevel metallization for embedded back end of the line structures Nov 6, 2002 Issued
Array ( [id] => 1299430 [patent_doc_number] => 06623995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Optimized monitor method for a metal patterning process' [patent_app_type] => B1 [patent_app_number] => 10/283437 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2198 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/623/06623995.pdf [firstpage_image] =>[orig_patent_app_number] => 10283437 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/283437
Optimized monitor method for a metal patterning process Oct 29, 2002 Issued
Array ( [id] => 6781177 [patent_doc_number] => 20030062624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Component built-in module and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/271937 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12326 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20030062624.pdf [firstpage_image] =>[orig_patent_app_number] => 10271937 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/271937
Method of manufacturing a component built-in module Oct 14, 2002 Issued
Array ( [id] => 1264528 [patent_doc_number] => 06660630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method for forming a tapered dual damascene via portion with improved performance' [patent_app_type] => B1 [patent_app_number] => 10/268511 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660630.pdf [firstpage_image] =>[orig_patent_app_number] => 10268511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268511
Method for forming a tapered dual damascene via portion with improved performance Oct 9, 2002 Issued
Array ( [id] => 7033754 [patent_doc_number] => 20050032264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/492061 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3925 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20050032264.pdf [firstpage_image] =>[orig_patent_app_number] => 10492061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/492061
Method of manufacturing a semiconductor device with outline of cleave marking regions and alignment or registration features Oct 6, 2002 Issued
Array ( [id] => 968521 [patent_doc_number] => 06939795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Selective dry etching of tantalum and tantalum nitride' [patent_app_type] => utility [patent_app_number] => 10/253791 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1340 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/939/06939795.pdf [firstpage_image] =>[orig_patent_app_number] => 10253791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/253791
Selective dry etching of tantalum and tantalum nitride Sep 22, 2002 Issued
Array ( [id] => 6772453 [patent_doc_number] => 20030015791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Semiconductor device and method of fabrication thereof, semiconductor module, circuit board, and electronic equipment' [patent_app_type] => new [patent_app_number] => 10/244162 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8676 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015791.pdf [firstpage_image] =>[orig_patent_app_number] => 10244162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/244162
Semiconductor device and method of fabrication thereof, semiconductor module, circuit board, and electronic equipment Sep 15, 2002 Issued
Array ( [id] => 6659746 [patent_doc_number] => 20030134509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/242422 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9379 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134509.pdf [firstpage_image] =>[orig_patent_app_number] => 10242422 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242422
Manufacturing method of semiconductor device Sep 12, 2002 Issued
Array ( [id] => 7135178 [patent_doc_number] => 20040043582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method and apparatus for simultaneously removing multiple conductive materials from microelectronic substrates' [patent_app_type] => new [patent_app_number] => 10/230602 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6126 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043582.pdf [firstpage_image] =>[orig_patent_app_number] => 10230602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230602
Method for simultaneously removing multiple conductive materials from microelectronic substrates Aug 28, 2002 Issued
Array ( [id] => 1123442 [patent_doc_number] => 06794284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Systems and methods for forming refractory metal nitride layers using disilazanes' [patent_app_type] => B2 [patent_app_number] => 10/229802 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 8193 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794284.pdf [firstpage_image] =>[orig_patent_app_number] => 10229802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229802
Systems and methods for forming refractory metal nitride layers using disilazanes Aug 27, 2002 Issued
Array ( [id] => 1119784 [patent_doc_number] => 06797598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method for forming an epitaxial cobalt silicide layer on MOS devices' [patent_app_type] => B2 [patent_app_number] => 10/226101 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1224 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797598.pdf [firstpage_image] =>[orig_patent_app_number] => 10226101 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226101
Method for forming an epitaxial cobalt silicide layer on MOS devices Aug 21, 2002 Issued
Array ( [id] => 6785184 [patent_doc_number] => 20030136423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Semiconductor device production method and semiconductor device production apparatus' [patent_app_type] => new [patent_app_number] => 10/223456 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8499 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20030136423.pdf [firstpage_image] =>[orig_patent_app_number] => 10223456 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/223456
Semiconductor device production method and semiconductor device production apparatus Aug 19, 2002 Issued
Array ( [id] => 1326823 [patent_doc_number] => 06599767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method of avoiding bonding pad oxidation in manufacturing an OLED device' [patent_app_type] => B1 [patent_app_number] => 10/223212 [patent_app_country] => US [patent_app_date] => 2002-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2191 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599767.pdf [firstpage_image] =>[orig_patent_app_number] => 10223212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/223212
Method of avoiding bonding pad oxidation in manufacturing an OLED device Aug 19, 2002 Issued
Array ( [id] => 1141538 [patent_doc_number] => 06777318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Aluminum/copper clad interconnect layer for VLSI applications' [patent_app_type] => B2 [patent_app_number] => 10/222361 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1361 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777318.pdf [firstpage_image] =>[orig_patent_app_number] => 10222361 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222361
Aluminum/copper clad interconnect layer for VLSI applications Aug 15, 2002 Issued
Array ( [id] => 6772450 [patent_doc_number] => 20030015788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Process for making fine pitch connections between devices and structure made by the process' [patent_app_type] => new [patent_app_number] => 10/213872 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015788.pdf [firstpage_image] =>[orig_patent_app_number] => 10213872 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/213872
Process for making fine pitch connections between devices and structure made by the process Aug 5, 2002 Issued
Array ( [id] => 7400710 [patent_doc_number] => 20040023489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Method of controlling metal formation processes using ion implantation, and system for performing same' [patent_app_type] => new [patent_app_number] => 10/210932 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4208 [patent_no_of_claims] => 105 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023489.pdf [firstpage_image] =>[orig_patent_app_number] => 10210932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210932
Method of controlling metal formation processes using ion implantation, and system for performing same Aug 1, 2002 Issued
Array ( [id] => 6688553 [patent_doc_number] => 20030032278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'All dual damascene oxide etch process steps in one confined plasma chamber' [patent_app_type] => new [patent_app_number] => 10/210612 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2461 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20030032278.pdf [firstpage_image] =>[orig_patent_app_number] => 10210612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210612
All dual damascene oxide etch process steps in one confined plasma chamber Jul 30, 2002 Issued
Array ( [id] => 1062741 [patent_doc_number] => 06849485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device' [patent_app_type] => utility [patent_app_number] => 10/205791 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2734 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849485.pdf [firstpage_image] =>[orig_patent_app_number] => 10205791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205791
Process sequence and mask layout to reduce junction leakage for a dual gate MOSFET device Jul 25, 2002 Issued
Array ( [id] => 7634786 [patent_doc_number] => 06656832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties' [patent_app_type] => B1 [patent_app_number] => 10/205052 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5150 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656832.pdf [firstpage_image] =>[orig_patent_app_number] => 10205052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205052
Plasma treatment method for fabricating microelectronic fabrication having formed therein conductor layer with enhanced electrical properties Jul 24, 2002 Issued
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