Search

Reginald Alexander

Examiner (ID: 18804, Phone: (571)272-1395 , Office: P/3742 )

Most Active Art Unit
1761
Art Unit(s)
3742, 3405, 1761, 2402, 3761, 2899
Total Applications
4197
Issued Applications
3176
Pending Applications
252
Abandoned Applications
806

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16552833 [patent_doc_number] => 10885997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => One time programmable memory cell (OTP) including main OTP cell transistor, redundant OTP transistor, and access transistor [patent_app_type] => utility [patent_app_number] => 16/515287 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8510 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515287
One time programmable memory cell (OTP) including main OTP cell transistor, redundant OTP transistor, and access transistor Jul 17, 2019 Issued
Array ( [id] => 15299505 [patent_doc_number] => 20190392888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => INTERNAL WRITE LEVELING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/514819 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514819 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514819
Internal write leveling circuitry Jul 16, 2019 Issued
Array ( [id] => 16495532 [patent_doc_number] => 10861579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Array plate short repair [patent_app_type] => utility [patent_app_number] => 16/513018 [patent_app_country] => US [patent_app_date] => 2019-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 29073 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16513018 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/513018
Array plate short repair Jul 15, 2019 Issued
Array ( [id] => 15351147 [patent_doc_number] => 20200013465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => MULTI-DECK MEMORY DEVICE WITH ACCESS LINE AND DATA LINE SEGREGATION BETWEEN DECKS AND METHOD OF OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 16/512067 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512067 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512067
MULTI-DECK MEMORY DEVICE WITH ACCESS LINE AND DATA LINE SEGREGATION BETWEEN DECKS AND METHOD OF OPERATION THEREOF Jul 14, 2019 Abandoned
Array ( [id] => 15442237 [patent_doc_number] => 20200035302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => SRAM/ROM MEMORY RECONFIGURABLE BY SUBSTRATE POLARIZATION [patent_app_type] => utility [patent_app_number] => 16/510263 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/510263
3D SRAM/ROM with several superimposed layers and reconfigurable by transistor rear biasing Jul 11, 2019 Issued
Array ( [id] => 17499303 [patent_doc_number] => 11288009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Read sample offset bit determination using most probably decoder logic in a memory sub-system [patent_app_type] => utility [patent_app_number] => 16/507844 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6501 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507844
Read sample offset bit determination using most probably decoder logic in a memory sub-system Jul 9, 2019 Issued
Array ( [id] => 16609058 [patent_doc_number] => 10910071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Voltage generator and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/507205 [patent_app_country] => US [patent_app_date] => 2019-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10911 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16507205 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/507205
Voltage generator and method of operating the same Jul 9, 2019 Issued
Array ( [id] => 15045171 [patent_doc_number] => 20190333590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/505351 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/505351
Operating method of memory device using channel boosting before read or verify operation Jul 7, 2019 Issued
Array ( [id] => 17107241 [patent_doc_number] => 11127466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => Read data sorting method and storage device for sequentially transmitting read data of continuous logic block addresses to host [patent_app_type] => utility [patent_app_number] => 16/503641 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2710 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503641 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503641
Read data sorting method and storage device for sequentially transmitting read data of continuous logic block addresses to host Jul 4, 2019 Issued
Array ( [id] => 16502277 [patent_doc_number] => 10867671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-15 [patent_title] => Techniques for applying multiple voltage pulses to select a memory cell [patent_app_type] => utility [patent_app_number] => 16/460863 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 14663 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16460863 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/460863
Techniques for applying multiple voltage pulses to select a memory cell Jul 1, 2019 Issued
Array ( [id] => 16463967 [patent_doc_number] => 10847326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Microelectromechanical device, which can be used as non-volatile memory module or relay, and memory including a plurality of microelectromechanical devices [patent_app_type] => utility [patent_app_number] => 16/453737 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453737 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453737
Microelectromechanical device, which can be used as non-volatile memory module or relay, and memory including a plurality of microelectromechanical devices Jun 25, 2019 Issued
Array ( [id] => 14906253 [patent_doc_number] => 20190296892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/440477 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/440477
Apparatuses and methods for logic/memory devices Jun 12, 2019 Issued
Array ( [id] => 18155953 [patent_doc_number] => 11568942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Using internal block variables and known pattern information to perform dynamic erase operation in non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/625587 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16625587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/625587
Using internal block variables and known pattern information to perform dynamic erase operation in non-volatile memory May 30, 2019 Issued
Array ( [id] => 16293303 [patent_doc_number] => 10770156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Memory devices and methods for read disturb mitigation involving word line scans to detect localized read disturb effects and to determine error count in tracked sub sets of memory addresses [patent_app_type] => utility [patent_app_number] => 16/416177 [patent_app_country] => US [patent_app_date] => 2019-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16416177 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/416177
Memory devices and methods for read disturb mitigation involving word line scans to detect localized read disturb effects and to determine error count in tracked sub sets of memory addresses May 17, 2019 Issued
Array ( [id] => 16440135 [patent_doc_number] => 20200357462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => HIGH BANDWIDTH REGISTER FILE CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/406749 [patent_app_country] => US [patent_app_date] => 2019-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/406749
High bandwidth register file circuit with high port counts for reduced bitline delay May 7, 2019 Issued
Array ( [id] => 14750453 [patent_doc_number] => 20190258400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => MEMORY DEVICES CONFIGURED TO LATCH DATA FOR OUTPUT IN RESPONSE TO AN EDGE OF A CLOCK SIGNAL GENERATED IN RESPONSE TO AN EDGE OF ANOTHER CLOCK SIGNAL [patent_app_type] => utility [patent_app_number] => 16/398646 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398646 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/398646
Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal Apr 29, 2019 Issued
Array ( [id] => 16402058 [patent_doc_number] => 20200342916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-29 [patent_title] => Self-Timed Memory with Adaptive Voltage Scaling [patent_app_type] => utility [patent_app_number] => 16/397677 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397677
Self-timed memory with adaptive voltage scaling Apr 28, 2019 Issued
Array ( [id] => 14721897 [patent_doc_number] => 20190252012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/396215 [patent_app_country] => US [patent_app_date] => 2019-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396215 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/396215
Memory system capable of performing a data clock calibration operation Apr 25, 2019 Issued
Array ( [id] => 16495806 [patent_doc_number] => 10861858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Static random-access memory with capacitor which has finger-shaped protrudent portions and related fabrication method [patent_app_type] => utility [patent_app_number] => 16/395215 [patent_app_country] => US [patent_app_date] => 2019-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5741 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16395215 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/395215
Static random-access memory with capacitor which has finger-shaped protrudent portions and related fabrication method Apr 24, 2019 Issued
Array ( [id] => 14691111 [patent_doc_number] => 20190244671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => SENSE AMPLIFIER AND LATCH CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 16/387357 [patent_app_country] => US [patent_app_date] => 2019-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/387357
Sense amplifier having a sense transistor to which different voltages are applied during sensing and after sensing to correct a variation of the threshold voltage of the sense transistor Apr 16, 2019 Issued
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