Search

Reginald Alexander

Examiner (ID: 18804, Phone: (571)272-1395 , Office: P/3742 )

Most Active Art Unit
1761
Art Unit(s)
3742, 3405, 1761, 2402, 3761, 2899
Total Applications
4197
Issued Applications
3176
Pending Applications
252
Abandoned Applications
806

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11339383 [patent_doc_number] => 20160365139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'CIRCUIT TO IMPROVE SRAM STABILITY' [patent_app_type] => utility [patent_app_number] => 14/734525 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4662 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734525 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734525
Circuit to improve SRAM stability Jun 8, 2015 Issued
Array ( [id] => 12114832 [patent_doc_number] => 09870825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Nonvolatile memory device and method of programming the same' [patent_app_type] => utility [patent_app_number] => 14/733239 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 12051 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733239 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733239
Nonvolatile memory device and method of programming the same Jun 7, 2015 Issued
Array ( [id] => 11659922 [patent_doc_number] => 09672933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Threshold based multi-level cell programming for a non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 14/733583 [patent_app_country] => US [patent_app_date] => 2015-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 12639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14733583 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/733583
Threshold based multi-level cell programming for a non-volatile memory device Jun 7, 2015 Issued
Array ( [id] => 11028476 [patent_doc_number] => 20160225432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION AND METHOD FOR DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/732318 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6659 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732318 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732318
Semiconductor device performing refresh operation and method for driving the same Jun 4, 2015 Issued
Array ( [id] => 10752925 [patent_doc_number] => 20160099077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'TEST SYSTEM SIMULTANEOUSLY TESTING SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 14/731784 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731784 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731784
Test system simultaneously testing semiconductor devices Jun 4, 2015 Issued
Array ( [id] => 11328032 [patent_doc_number] => 20160358644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'LOW-POWER ROW-ORIENTED MEMORY WRITE ASSIST CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/731678 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6281 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14731678 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/731678
Low-power row-oriented memory write assist circuit Jun 4, 2015 Issued
Array ( [id] => 10472012 [patent_doc_number] => 20150357028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'Systems and Methods Involving Multi-Bank, Dual-Pipe Memory Circuitry' [patent_app_type] => utility [patent_app_number] => 14/732639 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14614 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732639 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732639
Systems and methods involving multi-bank, dual-pipe memory circuitry Jun 4, 2015 Issued
Array ( [id] => 11021664 [patent_doc_number] => 20160218619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'DATA PIN REFERENCE VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/730594 [patent_app_country] => US [patent_app_date] => 2015-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730594 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730594
DATA PIN REFERENCE VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME Jun 3, 2015 Abandoned
Array ( [id] => 15397909 [patent_doc_number] => 10539609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Method of converting high-level test specification language to low-level test implementation language [patent_app_type] => utility [patent_app_number] => 14/707199 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8553 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14707199 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/707199
Method of converting high-level test specification language to low-level test implementation language May 7, 2015 Issued
Array ( [id] => 12551382 [patent_doc_number] => 10013343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Apparatus and method of refreshing a memory area of a non-volatile memory unit used in an embedded system [patent_app_type] => utility [patent_app_number] => 14/707374 [patent_app_country] => US [patent_app_date] => 2015-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3124 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14707374 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/707374
Apparatus and method of refreshing a memory area of a non-volatile memory unit used in an embedded system May 7, 2015 Issued
Array ( [id] => 13754447 [patent_doc_number] => 10170175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Semiconductor device comprising memory devices each comprising sense amplifier and memory cell [patent_app_type] => utility [patent_app_number] => 14/705698 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 60 [patent_no_of_words] => 36952 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705698
Semiconductor device comprising memory devices each comprising sense amplifier and memory cell May 5, 2015 Issued
Array ( [id] => 13754447 [patent_doc_number] => 10170175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Semiconductor device comprising memory devices each comprising sense amplifier and memory cell [patent_app_type] => utility [patent_app_number] => 14/705698 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 60 [patent_no_of_words] => 36952 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705698
Semiconductor device comprising memory devices each comprising sense amplifier and memory cell May 5, 2015 Issued
Array ( [id] => 10817197 [patent_doc_number] => 20160163359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'DATA SENSE AMPLIFIER AND MEMORY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/705604 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8710 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705604 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705604
Data sense amplifier and a memory device with open or folded bit line structure May 5, 2015 Issued
Array ( [id] => 13754447 [patent_doc_number] => 10170175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Semiconductor device comprising memory devices each comprising sense amplifier and memory cell [patent_app_type] => utility [patent_app_number] => 14/705698 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 60 [patent_no_of_words] => 36952 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705698
Semiconductor device comprising memory devices each comprising sense amplifier and memory cell May 5, 2015 Issued
Array ( [id] => 13754447 [patent_doc_number] => 10170175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Semiconductor device comprising memory devices each comprising sense amplifier and memory cell [patent_app_type] => utility [patent_app_number] => 14/705698 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 60 [patent_no_of_words] => 36952 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705698
Semiconductor device comprising memory devices each comprising sense amplifier and memory cell May 5, 2015 Issued
Array ( [id] => 10817212 [patent_doc_number] => 20160163375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/705628 [patent_app_country] => US [patent_app_date] => 2015-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14705628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/705628
Memory device with open bit line structure which minimizes loading difference of sense amplifiers arranged outermost part May 5, 2015 Issued
Array ( [id] => 10802540 [patent_doc_number] => 20160148696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/703196 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10680 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14703196 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/703196
3D multi-layer non-volatile memory device with planar string and method of programming May 3, 2015 Issued
Array ( [id] => 11681118 [patent_doc_number] => 09679652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Threshold based multi-level cell programming for reliability improvement' [patent_app_type] => utility [patent_app_number] => 14/702770 [patent_app_country] => US [patent_app_date] => 2015-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 9749 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14702770 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/702770
Threshold based multi-level cell programming for reliability improvement May 3, 2015 Issued
Array ( [id] => 12088901 [patent_doc_number] => 09842633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Tracking and correction of timing signals' [patent_app_type] => utility [patent_app_number] => 14/692346 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7039 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14692346 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/692346
Tracking and correction of timing signals Apr 20, 2015 Issued
Array ( [id] => 10817209 [patent_doc_number] => 20160163372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND REFRESH CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/688749 [patent_app_country] => US [patent_app_date] => 2015-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4069 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14688749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/688749
Semiconductor memory device and refresh control method thereof Apr 15, 2015 Issued
Menu