Search

Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 984642 [patent_doc_number] => 06928530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Method and device for sequential readout of a memory with address jump' [patent_app_type] => utility [patent_app_number] => 10/081740 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1387 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/928/06928530.pdf [firstpage_image] =>[orig_patent_app_number] => 10081740 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/081740
Method and device for sequential readout of a memory with address jump Feb 21, 2002 Issued
Array ( [id] => 6836099 [patent_doc_number] => 20030163645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Automatic prefetch of pointers' [patent_app_type] => new [patent_app_number] => 10/080859 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3845 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163645.pdf [firstpage_image] =>[orig_patent_app_number] => 10080859 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080859
Automatic prefetch of pointers Feb 21, 2002 Issued
Array ( [id] => 6741639 [patent_doc_number] => 20030159008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method and apparatus to control memory accesses' [patent_app_type] => new [patent_app_number] => 10/079967 [patent_app_country] => US [patent_app_date] => 2002-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4053 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159008.pdf [firstpage_image] =>[orig_patent_app_number] => 10079967 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079967
Method and apparatus to control memory accesses Feb 20, 2002 Issued
Array ( [id] => 6741630 [patent_doc_number] => 20030158999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method and apparatus for maintaining cache coherency in a storage system' [patent_app_type] => new [patent_app_number] => 10/080397 [patent_app_country] => US [patent_app_date] => 2002-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5226 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20030158999.pdf [firstpage_image] =>[orig_patent_app_number] => 10080397 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080397
Method and apparatus for maintaining cache coherency in a storage system Feb 20, 2002 Issued
Array ( [id] => 5918715 [patent_doc_number] => 20020113635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Memory control circuit' [patent_app_type] => new [patent_app_number] => 10/072934 [patent_app_country] => US [patent_app_date] => 2002-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14207 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113635.pdf [firstpage_image] =>[orig_patent_app_number] => 10072934 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/072934
Memory control circuit Feb 11, 2002 Issued
Array ( [id] => 6844468 [patent_doc_number] => 20030149815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Buffer management system for managing the transfer of data into and out of a buffer in a disc drive' [patent_app_type] => new [patent_app_number] => 10/014057 [patent_app_country] => US [patent_app_date] => 2001-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20030149815.pdf [firstpage_image] =>[orig_patent_app_number] => 10014057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/014057
Buffer management system for managing the transfer of data into and out of a buffer in a disc drive Dec 6, 2001 Issued
Array ( [id] => 6675697 [patent_doc_number] => 20030061300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Dual port RAM communication protocol' [patent_app_type] => new [patent_app_number] => 09/965490 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6814 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061300.pdf [firstpage_image] =>[orig_patent_app_number] => 09965490 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965490
Dual port RAM communication protocol Sep 26, 2001 Issued
Array ( [id] => 757611 [patent_doc_number] => 07024517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'System and method for configuring data storage in accordance with workload requirements' [patent_app_type] => utility [patent_app_number] => 09/965431 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 5672 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/024/07024517.pdf [firstpage_image] =>[orig_patent_app_number] => 09965431 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965431
System and method for configuring data storage in accordance with workload requirements Sep 26, 2001 Issued
Array ( [id] => 6349149 [patent_doc_number] => 20020035705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'Information recording method, information recording device, and information storage medium' [patent_app_type] => new [patent_app_number] => 09/955102 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 81 [patent_no_of_words] => 55746 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20020035705.pdf [firstpage_image] =>[orig_patent_app_number] => 09955102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955102
Information recording device and a method of recording information by setting the recording area based on contiguous data area Sep 18, 2001 Issued
Array ( [id] => 6751971 [patent_doc_number] => 20030046492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Configurable memory array' [patent_app_type] => new [patent_app_number] => 09/940709 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5291 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20030046492.pdf [firstpage_image] =>[orig_patent_app_number] => 09940709 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940709
Configurable memory array Aug 27, 2001 Abandoned
Array ( [id] => 6632158 [patent_doc_number] => 20020065993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'TLB operations based on shared bit' [patent_app_type] => new [patent_app_number] => 09/932319 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11625 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20020065993.pdf [firstpage_image] =>[orig_patent_app_number] => 09932319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932319
TLB operations based on shared bit Aug 16, 2001 Issued
Array ( [id] => 6133913 [patent_doc_number] => 20020078268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Local memory with indicator bits to support concurrent DMA and CPU access' [patent_app_type] => new [patent_app_number] => 09/932381 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13631 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078268.pdf [firstpage_image] =>[orig_patent_app_number] => 09932381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932381
Local memory with indicator bits to support concurrent DMA and CPU access Aug 16, 2001 Issued
Array ( [id] => 5830465 [patent_doc_number] => 20020069332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Cache and DMA with a global valid bit' [patent_app_type] => new [patent_app_number] => 09/932794 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10274 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069332.pdf [firstpage_image] =>[orig_patent_app_number] => 09932794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932794
Cache and DMA with a global valid bit Aug 16, 2001 Issued
Array ( [id] => 999035 [patent_doc_number] => 06915387 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-05 [patent_title] => 'System and method for handling updates to memory in a distributed shared memory system' [patent_app_type] => utility [patent_app_number] => 09/910589 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 10833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915387.pdf [firstpage_image] =>[orig_patent_app_number] => 09910589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/910589
System and method for handling updates to memory in a distributed shared memory system Jul 19, 2001 Issued
Array ( [id] => 1037055 [patent_doc_number] => 06877029 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Method and apparatus for managing node controllers using partitions in a computer system' [patent_app_type] => utility [patent_app_number] => 09/910629 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1630 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877029.pdf [firstpage_image] =>[orig_patent_app_number] => 09910629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/910629
Method and apparatus for managing node controllers using partitions in a computer system Jul 19, 2001 Issued
Array ( [id] => 704794 [patent_doc_number] => 07069306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-27 [patent_title] => 'Providing shared and non-shared access to memory in a system with plural processor coherence domains' [patent_app_type] => utility [patent_app_number] => 09/910591 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5273 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069306.pdf [firstpage_image] =>[orig_patent_app_number] => 09910591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/910591
Providing shared and non-shared access to memory in a system with plural processor coherence domains Jul 19, 2001 Issued
Array ( [id] => 1066479 [patent_doc_number] => 06850964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Methods for increasing cache capacity utilizing delta data' [patent_app_type] => utility [patent_app_number] => 09/891707 [patent_app_country] => US [patent_app_date] => 2001-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4110 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/850/06850964.pdf [firstpage_image] =>[orig_patent_app_number] => 09891707 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/891707
Methods for increasing cache capacity utilizing delta data Jun 25, 2001 Issued
Array ( [id] => 1001683 [patent_doc_number] => 06912618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Direct logical block addressing flash memory mass storage architecture' [patent_app_type] => utility [patent_app_number] => 09/850790 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4158 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912618.pdf [firstpage_image] =>[orig_patent_app_number] => 09850790 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850790
Direct logical block addressing flash memory mass storage architecture May 6, 2001 Issued
Array ( [id] => 6293818 [patent_doc_number] => 20020055929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Computer system with multiple heaps' [patent_app_type] => new [patent_app_number] => 09/845553 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16624 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055929.pdf [firstpage_image] =>[orig_patent_app_number] => 09845553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845553
Computer system with multiple heaps Apr 29, 2001 Issued
Array ( [id] => 1602248 [patent_doc_number] => 06493799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Word selection logic to implement an 80 or 96-bit cache SRAM' [patent_app_type] => B2 [patent_app_number] => 09/841643 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 4150 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493799.pdf [firstpage_image] =>[orig_patent_app_number] => 09841643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841643
Word selection logic to implement an 80 or 96-bit cache SRAM Apr 23, 2001 Issued
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