
Reginald Glenwood Bragdon
Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )
| Most Active Art Unit | 2751 |
| Art Unit(s) | 2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787 |
| Total Applications | 790 |
| Issued Applications | 531 |
| Pending Applications | 75 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1353212
[patent_doc_number] => 06594734
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Method and apparatus for self modifying code detection using a translation lookaside buffer'
[patent_app_type] => B1
[patent_app_number] => 09/466687
[patent_app_country] => US
[patent_app_date] => 1999-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/594/06594734.pdf
[firstpage_image] =>[orig_patent_app_number] => 09466687
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/466687 | Method and apparatus for self modifying code detection using a translation lookaside buffer | Dec 19, 1999 | Issued |
Array
(
[id] => 1595883
[patent_doc_number] => 06484238
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-19
[patent_title] => 'Apparatus and method for detecting snoop hits on victim lines issued to a higher level cache'
[patent_app_type] => B1
[patent_app_number] => 09/467352
[patent_app_country] => US
[patent_app_date] => 1999-12-20
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Array
(
[id] => 7645903
[patent_doc_number] => 06477620
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[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Cache-level return data by-pass system for a hierarchical memory'
[patent_app_type] => B1
[patent_app_number] => 09/467190
[patent_app_country] => US
[patent_app_date] => 1999-12-20
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[firstpage_image] =>[orig_patent_app_number] => 09467190
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/467190 | Cache-level return data by-pass system for a hierarchical memory | Dec 19, 1999 | Issued |
Array
(
[id] => 1456718
[patent_doc_number] => 06457095
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Method and apparatus for synchronizing dynamic random access memory exiting from a low power state'
[patent_app_type] => B1
[patent_app_number] => 09/458833
[patent_app_country] => US
[patent_app_date] => 1999-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/458833 | Method and apparatus for synchronizing dynamic random access memory exiting from a low power state | Dec 12, 1999 | Issued |
Array
(
[id] => 1539152
[patent_doc_number] => 06412044
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Cache memory system with dual cache tag memories'
[patent_app_type] => B1
[patent_app_number] => 09/457078
[patent_app_country] => US
[patent_app_date] => 1999-12-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/457078 | Cache memory system with dual cache tag memories | Dec 8, 1999 | Issued |
Array
(
[id] => 1357140
[patent_doc_number] => 06591350
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-08
[patent_title] => 'System and method for dynamically controlling memory access prioritization'
[patent_app_type] => B1
[patent_app_number] => 09/453988
[patent_app_country] => US
[patent_app_date] => 1999-12-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/591/06591350.pdf
[firstpage_image] =>[orig_patent_app_number] => 09453988
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/453988 | System and method for dynamically controlling memory access prioritization | Dec 1, 1999 | Issued |
Array
(
[id] => 1484942
[patent_doc_number] => 06453381
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'DDR DRAM data coherence scheme'
[patent_app_type] => B1
[patent_app_number] => 09/453045
[patent_app_country] => US
[patent_app_date] => 1999-12-02
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[pdf_file] => patents/06/453/06453381.pdf
[firstpage_image] =>[orig_patent_app_number] => 09453045
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/453045 | DDR DRAM data coherence scheme | Dec 1, 1999 | Issued |
Array
(
[id] => 7629999
[patent_doc_number] => 06636940
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-21
[patent_title] => 'Task control for high level commands in disk drives'
[patent_app_type] => B1
[patent_app_number] => 09/453382
[patent_app_country] => US
[patent_app_date] => 1999-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/06/636/06636940.pdf
[firstpage_image] =>[orig_patent_app_number] => 09453382
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/453382 | Task control for high level commands in disk drives | Dec 1, 1999 | Issued |
Array
(
[id] => 1521739
[patent_doc_number] => 06502177
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'Single cycle linear address calculation for relative branch addressing'
[patent_app_type] => B1
[patent_app_number] => 09/454076
[patent_app_country] => US
[patent_app_date] => 1999-12-02
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[pdf_file] => patents/06/502/06502177.pdf
[firstpage_image] =>[orig_patent_app_number] => 09454076
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/454076 | Single cycle linear address calculation for relative branch addressing | Dec 1, 1999 | Issued |
Array
(
[id] => 1604495
[patent_doc_number] => 06434681
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[patent_issue_date] => 2002-08-13
[patent_title] => 'Snapshot copy facility for a data storage system permitting continued host read/write access'
[patent_app_type] => B1
[patent_app_number] => 09/452964
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[patent_app_date] => 1999-12-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/434/06434681.pdf
[firstpage_image] =>[orig_patent_app_number] => 09452964
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/452964 | Snapshot copy facility for a data storage system permitting continued host read/write access | Dec 1, 1999 | Issued |
Array
(
[id] => 1557516
[patent_doc_number] => 06401169
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[patent_issue_date] => 2002-06-04
[patent_title] => 'Optical disc buffer under-run handling method'
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[patent_app_number] => 09/447964
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[pdf_file] => patents/06/401/06401169.pdf
[firstpage_image] =>[orig_patent_app_number] => 09447964
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/447964 | Optical disc buffer under-run handling method | Nov 22, 1999 | Issued |
Array
(
[id] => 1501533
[patent_doc_number] => 06405283
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[patent_issue_date] => 2002-06-11
[patent_title] => 'Method for handling buffer under-run during disc recording'
[patent_app_type] => B1
[patent_app_number] => 09/448030
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/448030 | Method for handling buffer under-run during disc recording | Nov 22, 1999 | Issued |
Array
(
[id] => 1430315
[patent_doc_number] => 06526474
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[patent_issue_date] => 2003-02-25
[patent_title] => 'Content addressable memory (CAM) with accesses to multiple CAM arrays used to generate result for various matching sizes'
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[patent_app_number] => 09/437012
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/437012 | Content addressable memory (CAM) with accesses to multiple CAM arrays used to generate result for various matching sizes | Nov 8, 1999 | Issued |
| 09/419523 | DETERMINING MEMORY UPGRADE OPTIONS | Oct 17, 1999 | Abandoned |
Array
(
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[patent_title] => 'Configuration in a configurable system on a chip'
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Array
(
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[patent_title] => 'Memory allocation system'
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[firstpage_image] =>[orig_patent_app_number] => 09418045
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/418045 | Memory allocation system | Oct 12, 1999 | Issued |
Array
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[patent_title] => 'Method, system, and program for performing read operations during a destage operation'
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Array
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