Search

Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1353212 [patent_doc_number] => 06594734 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method and apparatus for self modifying code detection using a translation lookaside buffer' [patent_app_type] => B1 [patent_app_number] => 09/466687 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8458 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594734.pdf [firstpage_image] =>[orig_patent_app_number] => 09466687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466687
Method and apparatus for self modifying code detection using a translation lookaside buffer Dec 19, 1999 Issued
Array ( [id] => 1595883 [patent_doc_number] => 06484238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Apparatus and method for detecting snoop hits on victim lines issued to a higher level cache' [patent_app_type] => B1 [patent_app_number] => 09/467352 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484238.pdf [firstpage_image] =>[orig_patent_app_number] => 09467352 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/467352
Apparatus and method for detecting snoop hits on victim lines issued to a higher level cache Dec 19, 1999 Issued
Array ( [id] => 7645903 [patent_doc_number] => 06477620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Cache-level return data by-pass system for a hierarchical memory' [patent_app_type] => B1 [patent_app_number] => 09/467190 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477620.pdf [firstpage_image] =>[orig_patent_app_number] => 09467190 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/467190
Cache-level return data by-pass system for a hierarchical memory Dec 19, 1999 Issued
Array ( [id] => 1456718 [patent_doc_number] => 06457095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for synchronizing dynamic random access memory exiting from a low power state' [patent_app_type] => B1 [patent_app_number] => 09/458833 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5509 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457095.pdf [firstpage_image] =>[orig_patent_app_number] => 09458833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458833
Method and apparatus for synchronizing dynamic random access memory exiting from a low power state Dec 12, 1999 Issued
Array ( [id] => 1539152 [patent_doc_number] => 06412044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Cache memory system with dual cache tag memories' [patent_app_type] => B1 [patent_app_number] => 09/457078 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2731 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 588 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412044.pdf [firstpage_image] =>[orig_patent_app_number] => 09457078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457078
Cache memory system with dual cache tag memories Dec 8, 1999 Issued
Array ( [id] => 1357140 [patent_doc_number] => 06591350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'System and method for dynamically controlling memory access prioritization' [patent_app_type] => B1 [patent_app_number] => 09/453988 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3496 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591350.pdf [firstpage_image] =>[orig_patent_app_number] => 09453988 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453988
System and method for dynamically controlling memory access prioritization Dec 1, 1999 Issued
Array ( [id] => 1484942 [patent_doc_number] => 06453381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'DDR DRAM data coherence scheme' [patent_app_type] => B1 [patent_app_number] => 09/453045 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2361 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453381.pdf [firstpage_image] =>[orig_patent_app_number] => 09453045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453045
DDR DRAM data coherence scheme Dec 1, 1999 Issued
Array ( [id] => 7629999 [patent_doc_number] => 06636940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Task control for high level commands in disk drives' [patent_app_type] => B1 [patent_app_number] => 09/453382 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3303 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636940.pdf [firstpage_image] =>[orig_patent_app_number] => 09453382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453382
Task control for high level commands in disk drives Dec 1, 1999 Issued
Array ( [id] => 1521739 [patent_doc_number] => 06502177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Single cycle linear address calculation for relative branch addressing' [patent_app_type] => B1 [patent_app_number] => 09/454076 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6870 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502177.pdf [firstpage_image] =>[orig_patent_app_number] => 09454076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454076
Single cycle linear address calculation for relative branch addressing Dec 1, 1999 Issued
Array ( [id] => 1604495 [patent_doc_number] => 06434681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Snapshot copy facility for a data storage system permitting continued host read/write access' [patent_app_type] => B1 [patent_app_number] => 09/452964 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 14049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434681.pdf [firstpage_image] =>[orig_patent_app_number] => 09452964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452964
Snapshot copy facility for a data storage system permitting continued host read/write access Dec 1, 1999 Issued
Array ( [id] => 1557516 [patent_doc_number] => 06401169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Optical disc buffer under-run handling method' [patent_app_type] => B1 [patent_app_number] => 09/447964 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5911 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401169.pdf [firstpage_image] =>[orig_patent_app_number] => 09447964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447964
Optical disc buffer under-run handling method Nov 22, 1999 Issued
Array ( [id] => 1501533 [patent_doc_number] => 06405283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for handling buffer under-run during disc recording' [patent_app_type] => B1 [patent_app_number] => 09/448030 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4328 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405283.pdf [firstpage_image] =>[orig_patent_app_number] => 09448030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448030
Method for handling buffer under-run during disc recording Nov 22, 1999 Issued
Array ( [id] => 1430315 [patent_doc_number] => 06526474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Content addressable memory (CAM) with accesses to multiple CAM arrays used to generate result for various matching sizes' [patent_app_type] => B1 [patent_app_number] => 09/437012 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3534 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526474.pdf [firstpage_image] =>[orig_patent_app_number] => 09437012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437012
Content addressable memory (CAM) with accesses to multiple CAM arrays used to generate result for various matching sizes Nov 8, 1999 Issued
09/419523 DETERMINING MEMORY UPGRADE OPTIONS Oct 17, 1999 Abandoned
Array ( [id] => 1066756 [patent_doc_number] => 06851047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Configuration in a configurable system on a chip' [patent_app_type] => utility [patent_app_number] => 09/419386 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5655 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851047.pdf [firstpage_image] =>[orig_patent_app_number] => 09419386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419386
Configuration in a configurable system on a chip Oct 14, 1999 Issued
Array ( [id] => 1423500 [patent_doc_number] => 06539456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Hardware acceleration of boot-up utilizing a non-volatile disk cache' [patent_app_type] => B2 [patent_app_number] => 09/417000 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1315 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539456.pdf [firstpage_image] =>[orig_patent_app_number] => 09417000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417000
Hardware acceleration of boot-up utilizing a non-volatile disk cache Oct 12, 1999 Issued
Array ( [id] => 1307983 [patent_doc_number] => 06629111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Memory allocation system' [patent_app_type] => B1 [patent_app_number] => 09/418045 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6433 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629111.pdf [firstpage_image] =>[orig_patent_app_number] => 09418045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418045
Memory allocation system Oct 12, 1999 Issued
Array ( [id] => 1587382 [patent_doc_number] => 06425050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method, system, and program for performing read operations during a destage operation' [patent_app_type] => B1 [patent_app_number] => 09/398381 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5439 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425050.pdf [firstpage_image] =>[orig_patent_app_number] => 09398381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398381
Method, system, and program for performing read operations during a destage operation Sep 16, 1999 Issued
Array ( [id] => 1490104 [patent_doc_number] => 06366983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method and system for symmetric memory population' [patent_app_type] => B1 [patent_app_number] => 09/396802 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2760 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366983.pdf [firstpage_image] =>[orig_patent_app_number] => 09396802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396802
Method and system for symmetric memory population Sep 13, 1999 Issued
Array ( [id] => 1604472 [patent_doc_number] => 06434658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Memory device operable with a small-capacity buffer memory and having a flash memory' [patent_app_type] => B1 [patent_app_number] => 09/395941 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 8229 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434658.pdf [firstpage_image] =>[orig_patent_app_number] => 09395941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395941
Memory device operable with a small-capacity buffer memory and having a flash memory Sep 13, 1999 Issued
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