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Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 1885, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2185, 2312, 2751, 2787, 2188, 2139, 2186
Total Applications
790
Issued Applications
533
Pending Applications
67
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7629999 [patent_doc_number] => 06636940 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Task control for high level commands in disk drives' [patent_app_type] => B1 [patent_app_number] => 09/453382 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3303 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636940.pdf [firstpage_image] =>[orig_patent_app_number] => 09453382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453382
Task control for high level commands in disk drives Dec 1, 1999 Issued
Array ( [id] => 1484942 [patent_doc_number] => 06453381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'DDR DRAM data coherence scheme' [patent_app_type] => B1 [patent_app_number] => 09/453045 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2361 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453381.pdf [firstpage_image] =>[orig_patent_app_number] => 09453045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453045
DDR DRAM data coherence scheme Dec 1, 1999 Issued
Array ( [id] => 1501533 [patent_doc_number] => 06405283 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for handling buffer under-run during disc recording' [patent_app_type] => B1 [patent_app_number] => 09/448030 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4328 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405283.pdf [firstpage_image] =>[orig_patent_app_number] => 09448030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/448030
Method for handling buffer under-run during disc recording Nov 22, 1999 Issued
Array ( [id] => 1557516 [patent_doc_number] => 06401169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Optical disc buffer under-run handling method' [patent_app_type] => B1 [patent_app_number] => 09/447964 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5911 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401169.pdf [firstpage_image] =>[orig_patent_app_number] => 09447964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447964
Optical disc buffer under-run handling method Nov 22, 1999 Issued
Array ( [id] => 1430315 [patent_doc_number] => 06526474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Content addressable memory (CAM) with accesses to multiple CAM arrays used to generate result for various matching sizes' [patent_app_type] => B1 [patent_app_number] => 09/437012 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3534 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526474.pdf [firstpage_image] =>[orig_patent_app_number] => 09437012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437012
Content addressable memory (CAM) with accesses to multiple CAM arrays used to generate result for various matching sizes Nov 8, 1999 Issued
09/419523 DETERMINING MEMORY UPGRADE OPTIONS Oct 17, 1999 Abandoned
Array ( [id] => 1066756 [patent_doc_number] => 06851047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-01 [patent_title] => 'Configuration in a configurable system on a chip' [patent_app_type] => utility [patent_app_number] => 09/419386 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5655 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/851/06851047.pdf [firstpage_image] =>[orig_patent_app_number] => 09419386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419386
Configuration in a configurable system on a chip Oct 14, 1999 Issued
Array ( [id] => 1307983 [patent_doc_number] => 06629111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Memory allocation system' [patent_app_type] => B1 [patent_app_number] => 09/418045 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6433 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629111.pdf [firstpage_image] =>[orig_patent_app_number] => 09418045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418045
Memory allocation system Oct 12, 1999 Issued
Array ( [id] => 1423500 [patent_doc_number] => 06539456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Hardware acceleration of boot-up utilizing a non-volatile disk cache' [patent_app_type] => B2 [patent_app_number] => 09/417000 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1315 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539456.pdf [firstpage_image] =>[orig_patent_app_number] => 09417000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417000
Hardware acceleration of boot-up utilizing a non-volatile disk cache Oct 12, 1999 Issued
Array ( [id] => 1587382 [patent_doc_number] => 06425050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method, system, and program for performing read operations during a destage operation' [patent_app_type] => B1 [patent_app_number] => 09/398381 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5439 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425050.pdf [firstpage_image] =>[orig_patent_app_number] => 09398381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398381
Method, system, and program for performing read operations during a destage operation Sep 16, 1999 Issued
Array ( [id] => 1604472 [patent_doc_number] => 06434658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Memory device operable with a small-capacity buffer memory and having a flash memory' [patent_app_type] => B1 [patent_app_number] => 09/395941 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 8229 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434658.pdf [firstpage_image] =>[orig_patent_app_number] => 09395941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395941
Memory device operable with a small-capacity buffer memory and having a flash memory Sep 13, 1999 Issued
Array ( [id] => 1490104 [patent_doc_number] => 06366983 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method and system for symmetric memory population' [patent_app_type] => B1 [patent_app_number] => 09/396802 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2760 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366983.pdf [firstpage_image] =>[orig_patent_app_number] => 09396802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396802
Method and system for symmetric memory population Sep 13, 1999 Issued
Array ( [id] => 1337042 [patent_doc_number] => 06604168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Flash eeprom management using ratio of used to unused sectors' [patent_app_type] => B2 [patent_app_number] => 09/350188 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 68 [patent_no_of_words] => 25377 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604168.pdf [firstpage_image] =>[orig_patent_app_number] => 09350188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350188
Flash eeprom management using ratio of used to unused sectors Jul 8, 1999 Issued
Array ( [id] => 1552835 [patent_doc_number] => 06446161 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Apparatus and method for reallocating logical to physical disk devices using a storage controller with access frequency and sequential access ratio calculations and display' [patent_app_type] => B1 [patent_app_number] => 09/335175 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5013 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446161.pdf [firstpage_image] =>[orig_patent_app_number] => 09335175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335175
Apparatus and method for reallocating logical to physical disk devices using a storage controller with access frequency and sequential access ratio calculations and display Jun 16, 1999 Issued
Array ( [id] => 1339176 [patent_doc_number] => 06601138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Apparatus system and method for N-way RAID controller having improved performance and fault tolerance' [patent_app_type] => B2 [patent_app_number] => 09/326497 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5552 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601138.pdf [firstpage_image] =>[orig_patent_app_number] => 09326497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326497
Apparatus system and method for N-way RAID controller having improved performance and fault tolerance Jun 3, 1999 Issued
Array ( [id] => 4374009 [patent_doc_number] => 06292871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Loading accessed data from a prefetch buffer to a least recently used position in a cache' [patent_app_type] => 1 [patent_app_number] => 9/318171 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5792 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292871.pdf [firstpage_image] =>[orig_patent_app_number] => 318171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318171
Loading accessed data from a prefetch buffer to a least recently used position in a cache May 24, 1999 Issued
Array ( [id] => 6181255 [patent_doc_number] => 20020156963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'DATA PROCESSING ARRANGEMENT AND MEMORY SYSTEM' [patent_app_type] => new [patent_app_number] => 09/316560 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4090 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20020156963.pdf [firstpage_image] =>[orig_patent_app_number] => 09316560 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316560
Data processing arrangement and memory system May 23, 1999 Issued
Array ( [id] => 1314367 [patent_doc_number] => 06622212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Adaptive prefetch of I/O data blocks' [patent_app_type] => B1 [patent_app_number] => 09/317442 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622212.pdf [firstpage_image] =>[orig_patent_app_number] => 09317442 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317442
Adaptive prefetch of I/O data blocks May 23, 1999 Issued
Array ( [id] => 4346274 [patent_doc_number] => 06330638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Synchronous audio DRAM storing audio and code data' [patent_app_type] => 1 [patent_app_number] => 9/316922 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2714 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330638.pdf [firstpage_image] =>[orig_patent_app_number] => 316922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316922
Synchronous audio DRAM storing audio and code data May 20, 1999 Issued
Array ( [id] => 4391637 [patent_doc_number] => 06289421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Intelligent memory devices for transferring data between electronic devices' [patent_app_type] => 1 [patent_app_number] => 9/316215 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3932 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289421.pdf [firstpage_image] =>[orig_patent_app_number] => 316215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316215
Intelligent memory devices for transferring data between electronic devices May 20, 1999 Issued
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