Reginald Glenwood Bragdon

Array ( [id] => 4412180 [patent_doc_number] => 06298411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method and apparatus to share instruction images in a virtual cache' [patent_app_type] => 1 [patent_app_number] => 9/225775 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3437 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298411.pdf [firstpage_image] =>[orig_patent_app_number] => 225775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6413908 [patent_doc_number] => 20020038407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'CIRCUIT ARRANGEMENT AND METHOD WITH STATE-BASED TRANSACTION SCHEDULING' [patent_app_type] => new [patent_app_number] => 09/225883 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7279 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038407.pdf [firstpage_image] =>[orig_patent_app_number] => 09225883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366103 [patent_doc_number] => 06286076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'High speed memory-based buffer and system and method for use thereof' [patent_app_type] => 1 [patent_app_number] => 9/225983 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8008 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286076.pdf [firstpage_image] =>[orig_patent_app_number] => 225983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4116066 [patent_doc_number] => 06067600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Combined cache tag and data memory architecture' [patent_app_type] => 1 [patent_app_number] => 9/221451 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2740 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/067/06067600.pdf [firstpage_image] =>[orig_patent_app_number] => 221451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252486 [patent_doc_number] => 06076145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Data supplying apparatus for independently performing hit determination and data access' [patent_app_type] => 1 [patent_app_number] => 9/211045 [patent_app_country] => US [patent_app_date] => 1998-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14491 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076145.pdf [firstpage_image] =>[orig_patent_app_number] => 211045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4021864 [patent_doc_number] => 05987563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Flash memory accessed using only the logical address' [patent_app_type] => 1 [patent_app_number] => 9/208474 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3921 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987563.pdf [firstpage_image] =>[orig_patent_app_number] => 208474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4257534 [patent_doc_number] => 06145053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Data security method using head disk stiction' [patent_app_type] => 1 [patent_app_number] => 9/205123 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2088 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145053.pdf [firstpage_image] =>[orig_patent_app_number] => 205123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466677 [patent_doc_number] => 06351797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Translation look-aside buffer for storing region configuration bits and method of operation' [patent_app_type] => B1 [patent_app_number] => 09/192122 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17830 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351797.pdf [firstpage_image] =>[orig_patent_app_number] => 09192122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6085527 [patent_doc_number] => 20020083276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'METHOD AND SYSTEM FOR SYNCHRONIZING BLOCK-ORGANIZED DATA TRANSFER AMONGST A PLURALITY OF PRODUCER AND CONSUMER STATIONS' [patent_app_type] => new [patent_app_number] => 09/182699 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1870 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083276.pdf [firstpage_image] =>[orig_patent_app_number] => 09182699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4162467 [patent_doc_number] => 06032240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Bypassing a nonpaged pool controller when accessing a remainder portion of a random access memory' [patent_app_type] => 1 [patent_app_number] => 9/178870 [patent_app_country] => US [patent_app_date] => 1998-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3393 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032240.pdf [firstpage_image] =>[orig_patent_app_number] => 178870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6283206 [patent_doc_number] => 20020108025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => ' MEMORY MANAGEMENT UNIT FOR JAVA ENVIRONMENT COMPUTERS' [patent_app_type] => new [patent_app_number] => 09/176530 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4564 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20020108025.pdf [firstpage_image] =>[orig_patent_app_number] => 09176530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4333169 [patent_doc_number] => 06332177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'N-way raid 1 on M drives block mapping' [patent_app_type] => 1 [patent_app_number] => 9/174790 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7415 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332177.pdf [firstpage_image] =>[orig_patent_app_number] => 174790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6878323 [patent_doc_number] => 20010002478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-31 [patent_title] => 'RAID STRIPING USING MULTIPLE VIRTUAL CHANNELS' [patent_app_type] => new-utility [patent_app_number] => 09/174580 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2199 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20010002478.pdf [firstpage_image] =>[orig_patent_app_number] => 09174580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422517 [patent_doc_number] => 06173373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and apparatus for implementing stable priority queues using concurrent non-blocking queuing techniques' [patent_app_type] => 1 [patent_app_number] => 9/173597 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4317 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173373.pdf [firstpage_image] =>[orig_patent_app_number] => 173597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4402217 [patent_doc_number] => 06279082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'System and method for efficient use of cache to improve access to memory of page type' [patent_app_type] => 1 [patent_app_number] => 9/173389 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5285 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279082.pdf [firstpage_image] =>[orig_patent_app_number] => 173389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4310198 [patent_doc_number] => 06212606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Computer system and method for establishing a standardized shared level for each storage unit' [patent_app_type] => 1 [patent_app_number] => 9/170965 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2737 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212606.pdf [firstpage_image] =>[orig_patent_app_number] => 170965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4021902 [patent_doc_number] => 05987566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Redundant storage with mirroring by logical volume with diverse reading process' [patent_app_type] => 1 [patent_app_number] => 9/167161 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9197 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987566.pdf [firstpage_image] =>[orig_patent_app_number] => 167161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1509006 [patent_doc_number] => 06467021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Data storage system storing data of varying block size' [patent_app_type] => B1 [patent_app_number] => 09/164344 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6278 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467021.pdf [firstpage_image] =>[orig_patent_app_number] => 09164344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147370 [patent_doc_number] => 06128695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Identification and verification of a sector within a block of mass storage flash memory' [patent_app_type] => 1 [patent_app_number] => 9/156951 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 13106 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128695.pdf [firstpage_image] =>[orig_patent_app_number] => 156951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4223908 [patent_doc_number] => 06078996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for increasing the speed of data processing in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/144677 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4594 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078996.pdf [firstpage_image] =>[orig_patent_app_number] => 144677 [rel_patent_id] =>[rel_patent_doc_number] =>)