
Reginald Glenwood Bragdon
Examiner (ID: 2350)
| Most Active Art Unit | 2751 |
| Art Unit(s) | 2751, 2188, 2189, 2186, 2787, 2312, 2185, 2139 |
| Total Applications | 790 |
| Issued Applications | 531 |
| Pending Applications | 74 |
| Abandoned Applications | 191 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 90/005086 | MEMORY APPARATUS AND METHOD CAPABLE OF SETTING ATTRIBUTE OF INFORMATION TO BE CACHED | Aug 25, 1998 | Issued |
Array
(
[id] => 4304713
[patent_doc_number] => 06269425
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-31
[patent_title] => 'Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system'
[patent_app_type] => 1
[patent_app_number] => 9/137548
[patent_app_country] => US
[patent_app_date] => 1998-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 9720
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/269/06269425.pdf
[firstpage_image] =>[orig_patent_app_number] => 137548
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/137548 | Accessing data from a multiple entry fully associative cache buffer in a multithread data processing system | Aug 19, 1998 | Issued |
Array
(
[id] => 4374062
[patent_doc_number] => 06175895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-16
[patent_title] => 'Cache enabling architecture'
[patent_app_type] => 1
[patent_app_number] => 9/135989
[patent_app_country] => US
[patent_app_date] => 1998-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1805
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/175/06175895.pdf
[firstpage_image] =>[orig_patent_app_number] => 135989
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/135989 | Cache enabling architecture | Aug 17, 1998 | Issued |
Array
(
[id] => 4379555
[patent_doc_number] => 06192448
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Structure and method for disk drive sizing using a disk drive controller coupled to a computer system'
[patent_app_type] => 1
[patent_app_number] => 9/136643
[patent_app_country] => US
[patent_app_date] => 1998-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7152
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/192/06192448.pdf
[firstpage_image] =>[orig_patent_app_number] => 136643
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/136643 | Structure and method for disk drive sizing using a disk drive controller coupled to a computer system | Aug 17, 1998 | Issued |
Array
(
[id] => 4254970
[patent_doc_number] => 06119200
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'System and method to protect SDRAM data during warm resets'
[patent_app_type] => 1
[patent_app_number] => 9/136239
[patent_app_country] => US
[patent_app_date] => 1998-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2409
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119200.pdf
[firstpage_image] =>[orig_patent_app_number] => 136239
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/136239 | System and method to protect SDRAM data during warm resets | Aug 17, 1998 | Issued |
Array
(
[id] => 4324568
[patent_doc_number] => 06327644
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-04
[patent_title] => 'Method and system for managing data in cache'
[patent_app_type] => 1
[patent_app_number] => 9/135842
[patent_app_country] => US
[patent_app_date] => 1998-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 6655
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/327/06327644.pdf
[firstpage_image] =>[orig_patent_app_number] => 135842
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/135842 | Method and system for managing data in cache | Aug 17, 1998 | Issued |
Array
(
[id] => 1178383
[patent_doc_number] => 06757705
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-29
[patent_title] => 'Method and system for client-side caching'
[patent_app_type] => B1
[patent_app_number] => 09/134720
[patent_app_country] => US
[patent_app_date] => 1998-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6073
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/757/06757705.pdf
[firstpage_image] =>[orig_patent_app_number] => 09134720
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/134720 | Method and system for client-side caching | Aug 13, 1998 | Issued |
Array
(
[id] => 4317656
[patent_doc_number] => 06185654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Phantom resource memory address mapping system'
[patent_app_type] => 1
[patent_app_number] => 9/118985
[patent_app_country] => US
[patent_app_date] => 1998-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 23
[patent_no_of_words] => 13778
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/185/06185654.pdf
[firstpage_image] =>[orig_patent_app_number] => 118985
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118985 | Phantom resource memory address mapping system | Jul 16, 1998 | Issued |
Array
(
[id] => 4427291
[patent_doc_number] => 06226714
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-01
[patent_title] => 'Method for invalidating cache lines on a sharing list'
[patent_app_type] => 1
[patent_app_number] => 9/121603
[patent_app_country] => US
[patent_app_date] => 1998-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5659
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/226/06226714.pdf
[firstpage_image] =>[orig_patent_app_number] => 121603
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121603 | Method for invalidating cache lines on a sharing list | Jul 8, 1998 | Issued |
Array
(
[id] => 4155821
[patent_doc_number] => 06122705
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Semiconductor memory device multiplying system clock for storing data different in data length'
[patent_app_type] => 1
[patent_app_number] => 9/110947
[patent_app_country] => US
[patent_app_date] => 1998-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3620
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/122/06122705.pdf
[firstpage_image] =>[orig_patent_app_number] => 110947
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110947 | Semiconductor memory device multiplying system clock for storing data different in data length | Jul 6, 1998 | Issued |
Array
(
[id] => 3947283
[patent_doc_number] => 05953737
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'Method and apparatus for performing erase operations transparent to a solid state storage system'
[patent_app_type] => 1
[patent_app_number] => 9/111414
[patent_app_country] => US
[patent_app_date] => 1998-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5187
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/953/05953737.pdf
[firstpage_image] =>[orig_patent_app_number] => 111414
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/111414 | Method and apparatus for performing erase operations transparent to a solid state storage system | Jul 6, 1998 | Issued |
Array
(
[id] => 4279983
[patent_doc_number] => 06205531
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method and apparatus for virtual address translation'
[patent_app_type] => 1
[patent_app_number] => 9/109476
[patent_app_country] => US
[patent_app_date] => 1998-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4647
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/205/06205531.pdf
[firstpage_image] =>[orig_patent_app_number] => 109476
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/109476 | Method and apparatus for virtual address translation | Jul 1, 1998 | Issued |
Array
(
[id] => 4152533
[patent_doc_number] => 06148374
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'Multi-way cache expansion circuit architecture'
[patent_app_type] => 1
[patent_app_number] => 9/109583
[patent_app_country] => US
[patent_app_date] => 1998-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4307
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/148/06148374.pdf
[firstpage_image] =>[orig_patent_app_number] => 109583
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/109583 | Multi-way cache expansion circuit architecture | Jul 1, 1998 | Issued |
Array
(
[id] => 4422304
[patent_doc_number] => 06272586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Memory system having programmable control parameters'
[patent_app_type] => 1
[patent_app_number] => 9/103844
[patent_app_country] => US
[patent_app_date] => 1998-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 19315
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/272/06272586.pdf
[firstpage_image] =>[orig_patent_app_number] => 103844
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/103844 | Memory system having programmable control parameters | Jun 23, 1998 | Issued |
Array
(
[id] => 4123850
[patent_doc_number] => 06101573
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Bit line and/or match line partitioned content addressable memory'
[patent_app_type] => 1
[patent_app_number] => 9/096523
[patent_app_country] => US
[patent_app_date] => 1998-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2713
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/101/06101573.pdf
[firstpage_image] =>[orig_patent_app_number] => 096523
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/096523 | Bit line and/or match line partitioned content addressable memory | Jun 11, 1998 | Issued |
Array
(
[id] => 4238923
[patent_doc_number] => 06088765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Removable medium data storage apparatus, optical disk apparatus and data transfer control method'
[patent_app_type] => 1
[patent_app_number] => 9/093121
[patent_app_country] => US
[patent_app_date] => 1998-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 20
[patent_no_of_words] => 11274
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/088/06088765.pdf
[firstpage_image] =>[orig_patent_app_number] => 093121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/093121 | Removable medium data storage apparatus, optical disk apparatus and data transfer control method | Jun 7, 1998 | Issued |
Array
(
[id] => 1501522
[patent_doc_number] => 06405280
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-11
[patent_title] => 'Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence'
[patent_app_type] => B1
[patent_app_number] => 09/092548
[patent_app_country] => US
[patent_app_date] => 1998-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4758
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/405/06405280.pdf
[firstpage_image] =>[orig_patent_app_number] => 09092548
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/092548 | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence | Jun 4, 1998 | Issued |
Array
(
[id] => 1106238
[patent_doc_number] => 06816956
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-09
[patent_title] => 'User control of multiple memory heaps'
[patent_app_type] => B1
[patent_app_number] => 09/088747
[patent_app_country] => US
[patent_app_date] => 1998-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5521
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/816/06816956.pdf
[firstpage_image] =>[orig_patent_app_number] => 09088747
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088747 | User control of multiple memory heaps | Jun 1, 1998 | Issued |
Array
(
[id] => 4010997
[patent_doc_number] => 05920885
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Dynamic random access memory with a normal precharge mode and a priority precharge mode'
[patent_app_type] => 1
[patent_app_number] => 9/088535
[patent_app_country] => US
[patent_app_date] => 1998-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5383
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920885.pdf
[firstpage_image] =>[orig_patent_app_number] => 088535
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088535 | Dynamic random access memory with a normal precharge mode and a priority precharge mode | May 31, 1998 | Issued |
Array
(
[id] => 4298426
[patent_doc_number] => 06282603
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Memory with pipelined accessed and priority precharge'
[patent_app_type] => 1
[patent_app_number] => 9/088649
[patent_app_country] => US
[patent_app_date] => 1998-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5721
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/282/06282603.pdf
[firstpage_image] =>[orig_patent_app_number] => 088649
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/088649 | Memory with pipelined accessed and priority precharge | May 31, 1998 | Issued |