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Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4010997 [patent_doc_number] => 05920885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Dynamic random access memory with a normal precharge mode and a priority precharge mode' [patent_app_type] => 1 [patent_app_number] => 9/088535 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5383 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920885.pdf [firstpage_image] =>[orig_patent_app_number] => 088535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088535
Dynamic random access memory with a normal precharge mode and a priority precharge mode May 31, 1998 Issued
Array ( [id] => 4018395 [patent_doc_number] => 05924113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Direct logical block addressing flash memory mass storage architecture' [patent_app_type] => 1 [patent_app_number] => 9/087720 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4045 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924113.pdf [firstpage_image] =>[orig_patent_app_number] => 087720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087720
Direct logical block addressing flash memory mass storage architecture May 28, 1998 Issued
Array ( [id] => 4151864 [patent_doc_number] => 06035382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Circuit for receiving a command word for accessing a secure subkey' [patent_app_type] => 1 [patent_app_number] => 9/074040 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 36 [patent_no_of_words] => 6740 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035382.pdf [firstpage_image] =>[orig_patent_app_number] => 074040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/074040
Circuit for receiving a command word for accessing a secure subkey May 6, 1998 Issued
Array ( [id] => 4118317 [patent_doc_number] => 06098157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method for storing and updating information describing data traffic on a network' [patent_app_type] => 1 [patent_app_number] => 9/066803 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4774 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098157.pdf [firstpage_image] =>[orig_patent_app_number] => 066803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066803
Method for storing and updating information describing data traffic on a network Apr 23, 1998 Issued
Array ( [id] => 4374033 [patent_doc_number] => 06175893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'High bandwidth code/data access using slow memory' [patent_app_type] => 1 [patent_app_number] => 9/066077 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6064 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175893.pdf [firstpage_image] =>[orig_patent_app_number] => 066077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066077
High bandwidth code/data access using slow memory Apr 23, 1998 Issued
Array ( [id] => 4388156 [patent_doc_number] => 06275903 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Stack cache miss handling' [patent_app_type] => 1 [patent_app_number] => 9/064686 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 67 [patent_no_of_words] => 12136 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275903.pdf [firstpage_image] =>[orig_patent_app_number] => 064686 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064686
Stack cache miss handling Apr 21, 1998 Issued
Array ( [id] => 4273490 [patent_doc_number] => 06209060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Disk array device for ensuring stable operation when a constituent disk device is replaced' [patent_app_type] => 1 [patent_app_number] => 9/063012 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 10269 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209060.pdf [firstpage_image] =>[orig_patent_app_number] => 063012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063012
Disk array device for ensuring stable operation when a constituent disk device is replaced Apr 20, 1998 Issued
Array ( [id] => 4257601 [patent_doc_number] => 06145058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Device and method for controlling write-back of data in a cache memory connected to a storage' [patent_app_type] => 1 [patent_app_number] => 9/062654 [patent_app_country] => US [patent_app_date] => 1998-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8175 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/145/06145058.pdf [firstpage_image] =>[orig_patent_app_number] => 062654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062654
Device and method for controlling write-back of data in a cache memory connected to a storage Apr 19, 1998 Issued
Array ( [id] => 3955199 [patent_doc_number] => 05940855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'System and method for determining relative cache performance in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/053843 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8084 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940855.pdf [firstpage_image] =>[orig_patent_app_number] => 053843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/053843
System and method for determining relative cache performance in a computer system Mar 31, 1998 Issued
Array ( [id] => 4179152 [patent_doc_number] => 06115791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control' [patent_app_type] => 1 [patent_app_number] => 9/048577 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6220 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115791.pdf [firstpage_image] =>[orig_patent_app_number] => 048577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048577
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control Mar 25, 1998 Issued
08/981032 PERSONAL COMPUTER WITH AT LEAST ONE FLOPPY DISK DRIVE Mar 16, 1998 Abandoned
Array ( [id] => 1109737 [patent_doc_number] => 06813685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'System for storing data and method of controlling the writing of redundant data' [patent_app_type] => B1 [patent_app_number] => 09/042334 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6749 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/813/06813685.pdf [firstpage_image] =>[orig_patent_app_number] => 09042334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042334
System for storing data and method of controlling the writing of redundant data Mar 12, 1998 Issued
Array ( [id] => 1466173 [patent_doc_number] => 06393518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Controlling shared disk data in a duplexed computer unit' [patent_app_type] => B1 [patent_app_number] => 09/043195 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1840 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393518.pdf [firstpage_image] =>[orig_patent_app_number] => 09043195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/043195
Controlling shared disk data in a duplexed computer unit Mar 12, 1998 Issued
Array ( [id] => 6962831 [patent_doc_number] => 20010013089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'CACHE COHERENCE UNIT FOR INTERCONNECTING MULTIPROCESSOR NODES HAVING PIPELINED SNOOPY PROTOCOL' [patent_app_type] => new [patent_app_number] => 09/041568 [patent_app_country] => US [patent_app_date] => 1998-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4571 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013089.pdf [firstpage_image] =>[orig_patent_app_number] => 09041568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/041568
Cache coherence unit for interconnecting multiprocessor nodes having pipelined snoopy protocol Mar 11, 1998 Issued
Array ( [id] => 4373689 [patent_doc_number] => 06202128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method and system for pre-fetch cache interrogation using snoop port' [patent_app_type] => 1 [patent_app_number] => 9/038422 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4660 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202128.pdf [firstpage_image] =>[orig_patent_app_number] => 038422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038422
Method and system for pre-fetch cache interrogation using snoop port Mar 10, 1998 Issued
Array ( [id] => 4335114 [patent_doc_number] => 06243789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method and apparatus for executing a program stored in nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 9/028159 [patent_app_country] => US [patent_app_date] => 1998-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5830 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243789.pdf [firstpage_image] =>[orig_patent_app_number] => 028159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/028159
Method and apparatus for executing a program stored in nonvolatile memory Feb 22, 1998 Issued
Array ( [id] => 4423671 [patent_doc_number] => 06240487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Integrated cache buffers' [patent_app_type] => 1 [patent_app_number] => 9/025606 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3252 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240487.pdf [firstpage_image] =>[orig_patent_app_number] => 025606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025606
Integrated cache buffers Feb 17, 1998 Issued
Array ( [id] => 4092185 [patent_doc_number] => 05966720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Flash memory accessed using only the logical address' [patent_app_type] => 1 [patent_app_number] => 8/998073 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3921 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966720.pdf [firstpage_image] =>[orig_patent_app_number] => 998073 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998073
Flash memory accessed using only the logical address Dec 23, 1997 Issued
Array ( [id] => 1415695 [patent_doc_number] => 06549984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Multi-bus access cache' [patent_app_type] => B1 [patent_app_number] => 08/992200 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549984.pdf [firstpage_image] =>[orig_patent_app_number] => 08992200 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992200
Multi-bus access cache Dec 16, 1997 Issued
Array ( [id] => 4268995 [patent_doc_number] => 06138204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Multi bus access memory' [patent_app_type] => 1 [patent_app_number] => 8/992466 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4985 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138204.pdf [firstpage_image] =>[orig_patent_app_number] => 992466 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992466
Multi bus access memory Dec 16, 1997 Issued
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