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Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4162482 [patent_doc_number] => 06032241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Fast RAM for use in an address translation circuit and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/992355 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 15896 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032241.pdf [firstpage_image] =>[orig_patent_app_number] => 992355 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992355
Fast RAM for use in an address translation circuit and method of operation Dec 16, 1997 Issued
Array ( [id] => 4424146 [patent_doc_number] => 06301647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Real mode translation look-aside buffer and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/992346 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16799 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301647.pdf [firstpage_image] =>[orig_patent_app_number] => 992346 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992346
Real mode translation look-aside buffer and method of operation Dec 16, 1997 Issued
Array ( [id] => 4199921 [patent_doc_number] => 06021468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Cache coherency protocol with efficient write-through aliasing' [patent_app_type] => 1 [patent_app_number] => 8/992788 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021468.pdf [firstpage_image] =>[orig_patent_app_number] => 992788 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992788
Cache coherency protocol with efficient write-through aliasing Dec 16, 1997 Issued
Array ( [id] => 4424732 [patent_doc_number] => 06230239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method of data migration' [patent_app_type] => 1 [patent_app_number] => 8/988979 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5280 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230239.pdf [firstpage_image] =>[orig_patent_app_number] => 988979 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988979
Method of data migration Dec 10, 1997 Issued
Array ( [id] => 4156041 [patent_doc_number] => 06122718 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Column address counter with minus two subtractor for address compare' [patent_app_type] => 1 [patent_app_number] => 8/988730 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4812 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122718.pdf [firstpage_image] =>[orig_patent_app_number] => 988730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988730
Column address counter with minus two subtractor for address compare Dec 10, 1997 Issued
Array ( [id] => 7095062 [patent_doc_number] => 20010034811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'HOST-AVAILABLE DEVICE BLOCK MAP FOR OPTIMIZED FILE RETRIEVAL FROM SERPENTINE TAPE DRIVES' [patent_app_type] => new [patent_app_number] => 08/988042 [patent_app_country] => US [patent_app_date] => 1997-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4250 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034811.pdf [firstpage_image] =>[orig_patent_app_number] => 08988042 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988042
Host-available device block map for optimized file retrieval from serpentine tape drives Dec 9, 1997 Issued
Array ( [id] => 3967326 [patent_doc_number] => 05983325 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Dataless touch to open a memory page' [patent_app_type] => 1 [patent_app_number] => 8/987536 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8425 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983325.pdf [firstpage_image] =>[orig_patent_app_number] => 987536 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987536
Dataless touch to open a memory page Dec 8, 1997 Issued
Array ( [id] => 4027069 [patent_doc_number] => 05890213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Disk drive with cache having adaptively aged segments' [patent_app_type] => 1 [patent_app_number] => 8/984114 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 68 [patent_no_of_words] => 24908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890213.pdf [firstpage_image] =>[orig_patent_app_number] => 984114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984114
Disk drive with cache having adaptively aged segments Dec 2, 1997 Issued
Array ( [id] => 4412263 [patent_doc_number] => 06298418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Multiprocessor system and cache coherency control method' [patent_app_type] => 1 [patent_app_number] => 8/975671 [patent_app_country] => US [patent_app_date] => 1997-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 7102 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298418.pdf [firstpage_image] =>[orig_patent_app_number] => 975671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975671
Multiprocessor system and cache coherency control method Nov 27, 1997 Issued
Array ( [id] => 3908347 [patent_doc_number] => 05778436 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Predictive caching system and method based on memory access which previously followed a cache miss' [patent_app_type] => 1 [patent_app_number] => 8/978320 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6616 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778436.pdf [firstpage_image] =>[orig_patent_app_number] => 978320 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978320
Predictive caching system and method based on memory access which previously followed a cache miss Nov 24, 1997 Issued
Array ( [id] => 4176710 [patent_doc_number] => 06157987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Pixel engine data caching mechanism' [patent_app_type] => 1 [patent_app_number] => 8/976748 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 7073 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157987.pdf [firstpage_image] =>[orig_patent_app_number] => 976748 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976748
Pixel engine data caching mechanism Nov 23, 1997 Issued
Array ( [id] => 3932774 [patent_doc_number] => 06003111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Bank state tracking method and device' [patent_app_type] => 1 [patent_app_number] => 8/974320 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4380 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003111.pdf [firstpage_image] =>[orig_patent_app_number] => 974320 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974320
Bank state tracking method and device Nov 18, 1997 Issued
Array ( [id] => 4032613 [patent_doc_number] => 05907859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Storage device in which read/write operation is controlled in response to source voltage' [patent_app_type] => 1 [patent_app_number] => 8/971469 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 11255 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907859.pdf [firstpage_image] =>[orig_patent_app_number] => 971469 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971469
Storage device in which read/write operation is controlled in response to source voltage Nov 16, 1997 Issued
Array ( [id] => 4162396 [patent_doc_number] => 06032235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Memory initialization circuit' [patent_app_type] => 1 [patent_app_number] => 8/970667 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4607 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032235.pdf [firstpage_image] =>[orig_patent_app_number] => 970667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970667
Memory initialization circuit Nov 13, 1997 Issued
Array ( [id] => 1602009 [patent_doc_number] => 06385704 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Accessing shared memory using token bit held by default by a single processor' [patent_app_type] => B1 [patent_app_number] => 08/969884 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 9049 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385704.pdf [firstpage_image] =>[orig_patent_app_number] => 08969884 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969884
Accessing shared memory using token bit held by default by a single processor Nov 13, 1997 Issued
Array ( [id] => 4025146 [patent_doc_number] => 06006307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Computer system employing a mirrored memory system for providing prefetch bandwidth' [patent_app_type] => 1 [patent_app_number] => 8/970042 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3591 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006307.pdf [firstpage_image] =>[orig_patent_app_number] => 970042 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970042
Computer system employing a mirrored memory system for providing prefetch bandwidth Nov 12, 1997 Issued
Array ( [id] => 4236903 [patent_doc_number] => 06112255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method and means for managing disk drive level logic and buffer modified access paths for enhanced raid array data rebuild and write update operations' [patent_app_type] => 1 [patent_app_number] => 8/969193 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6021 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/112/06112255.pdf [firstpage_image] =>[orig_patent_app_number] => 969193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969193
Method and means for managing disk drive level logic and buffer modified access paths for enhanced raid array data rebuild and write update operations Nov 12, 1997 Issued
Array ( [id] => 4423697 [patent_doc_number] => 06240491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Process and system for switching between an update and invalidate mode for each cache block' [patent_app_type] => 1 [patent_app_number] => 8/968424 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 7360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240491.pdf [firstpage_image] =>[orig_patent_app_number] => 968424 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968424
Process and system for switching between an update and invalidate mode for each cache block Nov 11, 1997 Issued
Array ( [id] => 3970433 [patent_doc_number] => 05991848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Computing system accessible to a split line on border of two pages within one cycle' [patent_app_type] => 1 [patent_app_number] => 8/964135 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4002 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 375 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991848.pdf [firstpage_image] =>[orig_patent_app_number] => 964135 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964135
Computing system accessible to a split line on border of two pages within one cycle Nov 5, 1997 Issued
Array ( [id] => 4133192 [patent_doc_number] => 06047359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Predictive read cache memories for reducing primary cache miss latency in embedded microprocessor systems' [patent_app_type] => 1 [patent_app_number] => 8/964046 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8946 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047359.pdf [firstpage_image] =>[orig_patent_app_number] => 964046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964046
Predictive read cache memories for reducing primary cache miss latency in embedded microprocessor systems Nov 3, 1997 Issued
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