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Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3961584 [patent_doc_number] => 05974510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method for testing the non-cacheable region functioning of a cache memory controller' [patent_app_type] => 1 [patent_app_number] => 8/962361 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4226 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/974/05974510.pdf [firstpage_image] =>[orig_patent_app_number] => 962361 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962361
Method for testing the non-cacheable region functioning of a cache memory controller Oct 30, 1997 Issued
Array ( [id] => 4167140 [patent_doc_number] => 06065092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Independent and cooperative multichannel memory architecture for use with master device' [patent_app_type] => 1 [patent_app_number] => 8/959280 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 28511 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065092.pdf [firstpage_image] =>[orig_patent_app_number] => 959280 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959280
Independent and cooperative multichannel memory architecture for use with master device Oct 23, 1997 Issued
Array ( [id] => 3798291 [patent_doc_number] => 05809537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Method and system for simultaneous processing of snoop and cache operations' [patent_app_type] => 1 [patent_app_number] => 8/957399 [patent_app_country] => US [patent_app_date] => 1997-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6238 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809537.pdf [firstpage_image] =>[orig_patent_app_number] => 957399 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/957399
Method and system for simultaneous processing of snoop and cache operations Oct 22, 1997 Issued
Array ( [id] => 4027139 [patent_doc_number] => 05890218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'System for allocating and accessing shared storage using program mode and DMA mode' [patent_app_type] => 1 [patent_app_number] => 8/954594 [patent_app_country] => US [patent_app_date] => 1997-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11357 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890218.pdf [firstpage_image] =>[orig_patent_app_number] => 954594 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954594
System for allocating and accessing shared storage using program mode and DMA mode Oct 19, 1997 Issued
Array ( [id] => 3960212 [patent_doc_number] => 05930815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Moving sequential sectors within a block of information in a flash memory mass storage architecture' [patent_app_type] => 1 [patent_app_number] => 8/946331 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 38 [patent_no_of_words] => 15926 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930815.pdf [firstpage_image] =>[orig_patent_app_number] => 946331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/946331
Moving sequential sectors within a block of information in a flash memory mass storage architecture Oct 6, 1997 Issued
Array ( [id] => 4203953 [patent_doc_number] => 06151657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Processor with embedded in-circuit programming structures' [patent_app_type] => 1 [patent_app_number] => 8/952045 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5288 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151657.pdf [firstpage_image] =>[orig_patent_app_number] => 952045 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/952045
Processor with embedded in-circuit programming structures Oct 2, 1997 Issued
Array ( [id] => 3765194 [patent_doc_number] => 05802552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'System and method for allocating and sharingpage buffers for a flash memory device' [patent_app_type] => 1 [patent_app_number] => 8/942187 [patent_app_country] => US [patent_app_date] => 1997-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 8069 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802552.pdf [firstpage_image] =>[orig_patent_app_number] => 942187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/942187
System and method for allocating and sharingpage buffers for a flash memory device Sep 30, 1997 Issued
Array ( [id] => 3967452 [patent_doc_number] => 05983331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor integrated circuit having a plurality of chips' [patent_app_type] => 1 [patent_app_number] => 8/943411 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5165 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983331.pdf [firstpage_image] =>[orig_patent_app_number] => 943411 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/943411
Semiconductor integrated circuit having a plurality of chips Sep 29, 1997 Issued
Array ( [id] => 4156837 [patent_doc_number] => RE036989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Virtual storage system and method' [patent_app_type] => 2 [patent_app_number] => 8/934732 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 12539 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036989.pdf [firstpage_image] =>[orig_patent_app_number] => 934732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934732
Virtual storage system and method Sep 21, 1997 Issued
Array ( [id] => 3907937 [patent_doc_number] => 05778411 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method for virtual to physical mapping in a mapped compressed virtual storage subsystem' [patent_app_type] => 1 [patent_app_number] => 8/933327 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14058 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778411.pdf [firstpage_image] =>[orig_patent_app_number] => 933327 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933327
Method for virtual to physical mapping in a mapped compressed virtual storage subsystem Sep 17, 1997 Issued
Array ( [id] => 4225756 [patent_doc_number] => 06029227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Disk control apparatus to perform parallel data transfer from a plurality of disk devices' [patent_app_type] => 1 [patent_app_number] => 8/932360 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5365 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/029/06029227.pdf [firstpage_image] =>[orig_patent_app_number] => 932360 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932360
Disk control apparatus to perform parallel data transfer from a plurality of disk devices Sep 16, 1997 Issued
Array ( [id] => 4373538 [patent_doc_number] => 06202118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Apparatus for address translation to selectively improve data transfer rates on a disk storage device' [patent_app_type] => 1 [patent_app_number] => 8/926797 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5852 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202118.pdf [firstpage_image] =>[orig_patent_app_number] => 926797 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/926797
Apparatus for address translation to selectively improve data transfer rates on a disk storage device Sep 9, 1997 Issued
Array ( [id] => 4160424 [patent_doc_number] => 06061760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Controller circuit apparatus for CD-ROM drives' [patent_app_type] => 1 [patent_app_number] => 8/927048 [patent_app_country] => US [patent_app_date] => 1997-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6912 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061760.pdf [firstpage_image] =>[orig_patent_app_number] => 927048 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927048
Controller circuit apparatus for CD-ROM drives Sep 9, 1997 Issued
Array ( [id] => 4422347 [patent_doc_number] => 06173359 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Storage and access to scratch mounts in VTS system' [patent_app_type] => 1 [patent_app_number] => 8/919043 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8568 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173359.pdf [firstpage_image] =>[orig_patent_app_number] => 919043 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919043
Storage and access to scratch mounts in VTS system Aug 26, 1997 Issued
Array ( [id] => 1540554 [patent_doc_number] => 06490657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Cache flush apparatus and computer system having the same' [patent_app_type] => B1 [patent_app_number] => 08/917530 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 32 [patent_no_of_words] => 18111 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490657.pdf [firstpage_image] =>[orig_patent_app_number] => 08917530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917530
Cache flush apparatus and computer system having the same Aug 25, 1997 Issued
Array ( [id] => 3967079 [patent_doc_number] => 05983309 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Autonomous high speed address translation with defect management for hard disc drives' [patent_app_type] => 1 [patent_app_number] => 8/917005 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 13289 [patent_no_of_claims] => 133 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983309.pdf [firstpage_image] =>[orig_patent_app_number] => 917005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917005
Autonomous high speed address translation with defect management for hard disc drives Aug 19, 1997 Issued
Array ( [id] => 4155785 [patent_doc_number] => 06122703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Generalized fourier transform processing system' [patent_app_type] => 1 [patent_app_number] => 8/912913 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7990 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122703.pdf [firstpage_image] =>[orig_patent_app_number] => 912913 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912913
Generalized fourier transform processing system Aug 14, 1997 Issued
Array ( [id] => 3971184 [patent_doc_number] => 06000017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Hybrid tag architecture for a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/909347 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2450 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000017.pdf [firstpage_image] =>[orig_patent_app_number] => 909347 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909347
Hybrid tag architecture for a cache memory Aug 10, 1997 Issued
Array ( [id] => 4064714 [patent_doc_number] => 05870568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Double buffering operations between the memory bus and the expansion bus of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/903949 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 15791 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/870/05870568.pdf [firstpage_image] =>[orig_patent_app_number] => 903949 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903949
Double buffering operations between the memory bus and the expansion bus of a computer system Jul 30, 1997 Issued
Array ( [id] => 4335170 [patent_doc_number] => 06243793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Protocol for arbitrating access to a shared memory area using historical state information' [patent_app_type] => 1 [patent_app_number] => 8/906134 [patent_app_country] => US [patent_app_date] => 1997-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5323 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243793.pdf [firstpage_image] =>[orig_patent_app_number] => 906134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/906134
Protocol for arbitrating access to a shared memory area using historical state information Jul 24, 1997 Issued
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