Search

Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3871019 [patent_doc_number] => 05706463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Cache coherent computer system that minimizes invalidation and copyback operations' [patent_app_type] => 1 [patent_app_number] => 8/854418 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3411 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706463.pdf [firstpage_image] =>[orig_patent_app_number] => 854418 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854418
Cache coherent computer system that minimizes invalidation and copyback operations May 11, 1997 Issued
Array ( [id] => 4058943 [patent_doc_number] => 05909692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'System and method for disk mapping and data retrieval' [patent_app_type] => 1 [patent_app_number] => 8/851701 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6956 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909692.pdf [firstpage_image] =>[orig_patent_app_number] => 851701 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851701
System and method for disk mapping and data retrieval May 5, 1997 Issued
Array ( [id] => 3803118 [patent_doc_number] => 05737570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Memory unit including an address generator' [patent_app_type] => 1 [patent_app_number] => 8/847907 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2721 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737570.pdf [firstpage_image] =>[orig_patent_app_number] => 847907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847907
Memory unit including an address generator Apr 27, 1997 Issued
Array ( [id] => 4071753 [patent_doc_number] => 05933859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Processor to memory interface logic for use in a computer system using a multiplexed memory address' [patent_app_type] => 1 [patent_app_number] => 8/846105 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3865 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933859.pdf [firstpage_image] =>[orig_patent_app_number] => 846105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/846105
Processor to memory interface logic for use in a computer system using a multiplexed memory address Apr 24, 1997 Issued
Array ( [id] => 3758693 [patent_doc_number] => 05787463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Disk array system including a dual-ported staging memory and concurrent redundancy calculation capability' [patent_app_type] => 1 [patent_app_number] => 8/834349 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3344 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/787/05787463.pdf [firstpage_image] =>[orig_patent_app_number] => 834349 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834349
Disk array system including a dual-ported staging memory and concurrent redundancy calculation capability Apr 14, 1997 Issued
Array ( [id] => 4026876 [patent_doc_number] => 05890200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests' [patent_app_type] => 1 [patent_app_number] => 8/825719 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9481 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890200.pdf [firstpage_image] =>[orig_patent_app_number] => 825719 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825719
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests Apr 3, 1997 Issued
Array ( [id] => 4059634 [patent_doc_number] => 05875467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests' [patent_app_type] => 1 [patent_app_number] => 8/826556 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9478 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875467.pdf [firstpage_image] =>[orig_patent_app_number] => 826556 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826556
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests Apr 3, 1997 Issued
Array ( [id] => 4011503 [patent_doc_number] => 05893151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests' [patent_app_type] => 1 [patent_app_number] => 8/826553 [patent_app_country] => US [patent_app_date] => 1997-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9478 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893151.pdf [firstpage_image] =>[orig_patent_app_number] => 826553 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826553
Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests Apr 3, 1997 Issued
Array ( [id] => 4032562 [patent_doc_number] => 05907856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Moving sectors within a block of information in a flash memory mass storage architecture' [patent_app_type] => 1 [patent_app_number] => 8/831266 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 11147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907856.pdf [firstpage_image] =>[orig_patent_app_number] => 831266 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/831266
Moving sectors within a block of information in a flash memory mass storage architecture Mar 30, 1997 Issued
Array ( [id] => 3816056 [patent_doc_number] => 05829050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Memory control device and memory data search circuit' [patent_app_type] => 1 [patent_app_number] => 8/822823 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 20572 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829050.pdf [firstpage_image] =>[orig_patent_app_number] => 822823 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822823
Memory control device and memory data search circuit Mar 23, 1997 Issued
Array ( [id] => 3800330 [patent_doc_number] => 05819304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Random access memory assembly' [patent_app_type] => 1 [patent_app_number] => 8/823464 [patent_app_country] => US [patent_app_date] => 1997-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 73 [patent_no_of_words] => 26447 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819304.pdf [firstpage_image] =>[orig_patent_app_number] => 823464 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/823464
Random access memory assembly Mar 23, 1997 Issued
Array ( [id] => 3805984 [patent_doc_number] => 05822779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active' [patent_app_type] => 1 [patent_app_number] => 8/821416 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 8238 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822779.pdf [firstpage_image] =>[orig_patent_app_number] => 821416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821416
Microprocessor-based data processing apparatus that commences a next overlapping cycle when a ready signal is detected not to be active Mar 20, 1997 Issued
Array ( [id] => 6066284 [patent_doc_number] => 20020032827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'STRUCTURE AND METHOD FOR PROVIDING MULTIPLE EXTERNALLY ACCESSIBLE ON-CHIP CACHES IN A MICROPROCESSOR' [patent_app_type] => new [patent_app_number] => 08/818060 [patent_app_country] => US [patent_app_date] => 1997-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5307 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20020032827.pdf [firstpage_image] =>[orig_patent_app_number] => 08818060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/818060
Test mode accessing of an internal cache memory Mar 13, 1997 Issued
Array ( [id] => 3900971 [patent_doc_number] => 05806084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory' [patent_app_type] => 1 [patent_app_number] => 8/800507 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 9696 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/806/05806084.pdf [firstpage_image] =>[orig_patent_app_number] => 800507 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800507
Space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory Feb 13, 1997 Issued
Array ( [id] => 1210175 [patent_doc_number] => 06718375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Using local storage to handle multiple outstanding requests in a SCI system' [patent_app_type] => B1 [patent_app_number] => 08/797674 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2850 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718375.pdf [firstpage_image] =>[orig_patent_app_number] => 08797674 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797674
Using local storage to handle multiple outstanding requests in a SCI system Jan 30, 1997 Issued
Array ( [id] => 3900921 [patent_doc_number] => 05749092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Method and apparatus for using a direct memory access unit and a data cache unit in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/789455 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4674 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/749/05749092.pdf [firstpage_image] =>[orig_patent_app_number] => 789455 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789455
Method and apparatus for using a direct memory access unit and a data cache unit in a microprocessor Jan 26, 1997 Issued
Array ( [id] => 3833264 [patent_doc_number] => 05813023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method and apparatus for multiple latency synchronous dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/783922 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12630 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813023.pdf [firstpage_image] =>[orig_patent_app_number] => 783922 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783922
Method and apparatus for multiple latency synchronous dynamic random access memory Jan 16, 1997 Issued
Array ( [id] => 4019803 [patent_doc_number] => 05860115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Requesting a dump of information stored within a coupling facility, in which the dump includes serviceability information from an operating system that lost communication with the coupling facility' [patent_app_type] => 1 [patent_app_number] => 8/779195 [patent_app_country] => US [patent_app_date] => 1997-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 54 [patent_no_of_words] => 30202 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860115.pdf [firstpage_image] =>[orig_patent_app_number] => 779195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/779195
Requesting a dump of information stored within a coupling facility, in which the dump includes serviceability information from an operating system that lost communication with the coupling facility Jan 5, 1997 Issued
Array ( [id] => 3954841 [patent_doc_number] => 05900014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'External means of overriding and controlling cacheability attribute of selected CPU accesses to monitor instruction and data streams' [patent_app_type] => 1 [patent_app_number] => 8/769321 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10565 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900014.pdf [firstpage_image] =>[orig_patent_app_number] => 769321 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769321
External means of overriding and controlling cacheability attribute of selected CPU accesses to monitor instruction and data streams Dec 18, 1996 Issued
Array ( [id] => 3901066 [patent_doc_number] => 05715424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Apparatus and method for writing data onto rewritable optical media' [patent_app_type] => 1 [patent_app_number] => 8/763876 [patent_app_country] => US [patent_app_date] => 1996-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3704 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715424.pdf [firstpage_image] =>[orig_patent_app_number] => 763876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763876
Apparatus and method for writing data onto rewritable optical media Dec 10, 1996 Issued
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