Search

Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3743849 [patent_doc_number] => 05666515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address' [patent_app_type] => 1 [patent_app_number] => 8/759996 [patent_app_country] => US [patent_app_date] => 1996-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6922 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666515.pdf [firstpage_image] =>[orig_patent_app_number] => 759996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759996
Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address Dec 3, 1996 Issued
Array ( [id] => 4059438 [patent_doc_number] => 05875455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Information recording and reproducing apparatus merging sequential recording requests into a single recording request, and method of data caching for such apparatus' [patent_app_type] => 1 [patent_app_number] => 8/756759 [patent_app_country] => US [patent_app_date] => 1996-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 36 [patent_no_of_words] => 12518 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875455.pdf [firstpage_image] =>[orig_patent_app_number] => 756759 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756759
Information recording and reproducing apparatus merging sequential recording requests into a single recording request, and method of data caching for such apparatus Nov 25, 1996 Issued
Array ( [id] => 3765977 [patent_doc_number] => 05802605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Physical address size selection and page size selection in an address translator' [patent_app_type] => 1 [patent_app_number] => 8/756184 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7550 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802605.pdf [firstpage_image] =>[orig_patent_app_number] => 756184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756184
Physical address size selection and page size selection in an address translator Nov 24, 1996 Issued
Array ( [id] => 4020460 [patent_doc_number] => 05860158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Cache control unit with a cache request transaction-oriented protocol' [patent_app_type] => 1 [patent_app_number] => 8/751149 [patent_app_country] => US [patent_app_date] => 1996-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10877 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860158.pdf [firstpage_image] =>[orig_patent_app_number] => 751149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751149
Cache control unit with a cache request transaction-oriented protocol Nov 14, 1996 Issued
08/749312 HIGH PERFORMANCE DATA PATH WITH XOR ON THE FLY Nov 13, 1996 Abandoned
Array ( [id] => 4133226 [patent_doc_number] => 06047362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Delayed removal of address mapping for terminated processes' [patent_app_type] => 1 [patent_app_number] => 8/744447 [patent_app_country] => US [patent_app_date] => 1996-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 11948 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/047/06047362.pdf [firstpage_image] =>[orig_patent_app_number] => 744447 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/744447
Delayed removal of address mapping for terminated processes Nov 7, 1996 Issued
08/737295 DATA CACHE Nov 7, 1996 Abandoned
Array ( [id] => 3798373 [patent_doc_number] => 05809543 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Fault tolerant extended processing complex for redundant nonvolatile file caching' [patent_app_type] => 1 [patent_app_number] => 8/745111 [patent_app_country] => US [patent_app_date] => 1996-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 76 [patent_no_of_words] => 43577 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809543.pdf [firstpage_image] =>[orig_patent_app_number] => 745111 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/745111
Fault tolerant extended processing complex for redundant nonvolatile file caching Nov 6, 1996 Issued
Array ( [id] => 3872337 [patent_doc_number] => 05768558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle' [patent_app_type] => 1 [patent_app_number] => 8/734728 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4526 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/768/05768558.pdf [firstpage_image] =>[orig_patent_app_number] => 734728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/734728
Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle Oct 20, 1996 Issued
08/729339 MECHANISM FOR SHARING PAGE BUFFERS IN A MEMORY DEVICE Oct 15, 1996 Abandoned
Array ( [id] => 3836381 [patent_doc_number] => 05790828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Disk meshing and flexible storage mapping with enhanced flexible caching' [patent_app_type] => 1 [patent_app_number] => 8/724149 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 15607 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790828.pdf [firstpage_image] =>[orig_patent_app_number] => 724149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724149
Disk meshing and flexible storage mapping with enhanced flexible caching Sep 29, 1996 Issued
Array ( [id] => 4026949 [patent_doc_number] => 05890205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Optimized application installation using disk block relocation' [patent_app_type] => 1 [patent_app_number] => 8/721826 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3827 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890205.pdf [firstpage_image] =>[orig_patent_app_number] => 721826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721826
Optimized application installation using disk block relocation Sep 26, 1996 Issued
Array ( [id] => 4071577 [patent_doc_number] => 05933847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Selecting erase method based on type of power supply for flash EEPROM' [patent_app_type] => 1 [patent_app_number] => 8/710946 [patent_app_country] => US [patent_app_date] => 1996-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 68 [patent_no_of_words] => 20987 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933847.pdf [firstpage_image] =>[orig_patent_app_number] => 710946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710946
Selecting erase method based on type of power supply for flash EEPROM Sep 23, 1996 Issued
Array ( [id] => 4192478 [patent_doc_number] => 06141729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Data transfer system which divides data among transfer units having different transfer speed characteristics' [patent_app_type] => 1 [patent_app_number] => 8/723872 [patent_app_country] => US [patent_app_date] => 1996-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 8361 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141729.pdf [firstpage_image] =>[orig_patent_app_number] => 723872 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/723872
Data transfer system which divides data among transfer units having different transfer speed characteristics Sep 22, 1996 Issued
Array ( [id] => 3667456 [patent_doc_number] => 05623635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Memory consistent pre-ownership method and system for transferring data between and I/O device and a main memory' [patent_app_type] => 1 [patent_app_number] => 8/714888 [patent_app_country] => US [patent_app_date] => 1996-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9519 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/623/05623635.pdf [firstpage_image] =>[orig_patent_app_number] => 714888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714888
Memory consistent pre-ownership method and system for transferring data between and I/O device and a main memory Sep 16, 1996 Issued
Array ( [id] => 3888765 [patent_doc_number] => 05893927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Memory device having programmable device width, method of programming, and method of setting device width for memory device' [patent_app_type] => 1 [patent_app_number] => 8/713640 [patent_app_country] => US [patent_app_date] => 1996-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5236 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893927.pdf [firstpage_image] =>[orig_patent_app_number] => 713640 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/713640
Memory device having programmable device width, method of programming, and method of setting device width for memory device Sep 12, 1996 Issued
Array ( [id] => 4061130 [patent_doc_number] => 05895501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Virtual memory system for vector based computer systems' [patent_app_type] => 1 [patent_app_number] => 8/706806 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10457 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895501.pdf [firstpage_image] =>[orig_patent_app_number] => 706806 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/706806
Virtual memory system for vector based computer systems Sep 2, 1996 Issued
Array ( [id] => 4167210 [patent_doc_number] => 06065097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Apparatus and method for sharing a unified memory bus between external cache memory and primary memory' [patent_app_type] => 1 [patent_app_number] => 8/705400 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5015 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065097.pdf [firstpage_image] =>[orig_patent_app_number] => 705400 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705400
Apparatus and method for sharing a unified memory bus between external cache memory and primary memory Aug 28, 1996 Issued
Array ( [id] => 3918457 [patent_doc_number] => 05751988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Microcomputer with memory bank configuration and register bank configuration' [patent_app_type] => 1 [patent_app_number] => 8/705017 [patent_app_country] => US [patent_app_date] => 1996-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3450 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751988.pdf [firstpage_image] =>[orig_patent_app_number] => 705017 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/705017
Microcomputer with memory bank configuration and register bank configuration Aug 28, 1996 Issued
Array ( [id] => 3782611 [patent_doc_number] => 05850528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Bus timing protocol for a data storage system' [patent_app_type] => 1 [patent_app_number] => 8/701862 [patent_app_country] => US [patent_app_date] => 1996-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 8134 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850528.pdf [firstpage_image] =>[orig_patent_app_number] => 701862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/701862
Bus timing protocol for a data storage system Aug 22, 1996 Issued
Menu