Search

Reginald Glenwood Bragdon

Examiner (ID: 2350)

Most Active Art Unit
2751
Art Unit(s)
2751, 2188, 2189, 2186, 2787, 2312, 2185, 2139
Total Applications
790
Issued Applications
531
Pending Applications
74
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4011277 [patent_doc_number] => 05893139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Data storage device and storage method in which algorithms are provided for calculating access frequencies of data' [patent_app_type] => 1 [patent_app_number] => 8/681950 [patent_app_country] => US [patent_app_date] => 1996-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 9622 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893139.pdf [firstpage_image] =>[orig_patent_app_number] => 681950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681950
Data storage device and storage method in which algorithms are provided for calculating access frequencies of data Jul 29, 1996 Issued
Array ( [id] => 3991291 [patent_doc_number] => 05905996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Combined cache tag and data memory architecture' [patent_app_type] => 1 [patent_app_number] => 8/681674 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2706 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905996.pdf [firstpage_image] =>[orig_patent_app_number] => 681674 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681674
Combined cache tag and data memory architecture Jul 28, 1996 Issued
Array ( [id] => 3854540 [patent_doc_number] => 05708792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Method and apparatus for a coherent copy-back buffer in a multipressor computer system' [patent_app_type] => 1 [patent_app_number] => 8/681602 [patent_app_country] => US [patent_app_date] => 1996-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708792.pdf [firstpage_image] =>[orig_patent_app_number] => 681602 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/681602
Method and apparatus for a coherent copy-back buffer in a multipressor computer system Jul 28, 1996 Issued
Array ( [id] => 4151730 [patent_doc_number] => 06035375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Cache memory with an allocable micro-cache' [patent_app_type] => 1 [patent_app_number] => 8/683579 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5967 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035375.pdf [firstpage_image] =>[orig_patent_app_number] => 683579 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/683579
Cache memory with an allocable micro-cache Jul 14, 1996 Issued
Array ( [id] => 4022102 [patent_doc_number] => 05987578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Pipelining to improve the interface of memory devices' [patent_app_type] => 1 [patent_app_number] => 8/673062 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2285 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987578.pdf [firstpage_image] =>[orig_patent_app_number] => 673062 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673062
Pipelining to improve the interface of memory devices Jun 30, 1996 Issued
Array ( [id] => 4044771 [patent_doc_number] => 05903907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Skip-level write-through in a multi-level memory of a computer system' [patent_app_type] => 1 [patent_app_number] => 8/674560 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3396 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903907.pdf [firstpage_image] =>[orig_patent_app_number] => 674560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674560
Skip-level write-through in a multi-level memory of a computer system Jun 30, 1996 Issued
Array ( [id] => 3922743 [patent_doc_number] => 05752258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Encoding method for directory state in cache coherent distributed shared memory system' [patent_app_type] => 1 [patent_app_number] => 8/672946 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3993 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752258.pdf [firstpage_image] =>[orig_patent_app_number] => 672946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672946
Encoding method for directory state in cache coherent distributed shared memory system Jun 30, 1996 Issued
Array ( [id] => 3765336 [patent_doc_number] => 05802561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Simultaneous, mirror write cache' [patent_app_type] => 1 [patent_app_number] => 8/671154 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5760 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802561.pdf [firstpage_image] =>[orig_patent_app_number] => 671154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/671154
Simultaneous, mirror write cache Jun 27, 1996 Issued
Array ( [id] => 3974394 [patent_doc_number] => 05937174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Scalable hierarchial memory structure for high data bandwidth raid applications' [patent_app_type] => 1 [patent_app_number] => 8/673654 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6936 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937174.pdf [firstpage_image] =>[orig_patent_app_number] => 673654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673654
Scalable hierarchial memory structure for high data bandwidth raid applications Jun 27, 1996 Issued
Array ( [id] => 4223869 [patent_doc_number] => 06078993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Data supplying apparatus for independently performing hit determination and data access' [patent_app_type] => 1 [patent_app_number] => 8/672485 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14481 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078993.pdf [firstpage_image] =>[orig_patent_app_number] => 672485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/672485
Data supplying apparatus for independently performing hit determination and data access Jun 25, 1996 Issued
Array ( [id] => 4011339 [patent_doc_number] => 05893143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Parallel processing unit with cache memories storing NO-OP mask bits for instructions' [patent_app_type] => 1 [patent_app_number] => 8/667670 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 6339 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893143.pdf [firstpage_image] =>[orig_patent_app_number] => 667670 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/667670
Parallel processing unit with cache memories storing NO-OP mask bits for instructions Jun 20, 1996 Issued
Array ( [id] => 4006835 [patent_doc_number] => 05960453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Word selection logic to implement an 80 or 96-bit cache SRAM' [patent_app_type] => 1 [patent_app_number] => 8/663386 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 4186 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960453.pdf [firstpage_image] =>[orig_patent_app_number] => 663386 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663386
Word selection logic to implement an 80 or 96-bit cache SRAM Jun 12, 1996 Issued
Array ( [id] => 3734565 [patent_doc_number] => 05682515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Low power set associative cache memory with status inhibit of cache data output' [patent_app_type] => 1 [patent_app_number] => 8/664319 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4825 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 447 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682515.pdf [firstpage_image] =>[orig_patent_app_number] => 664319 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664319
Low power set associative cache memory with status inhibit of cache data output Jun 9, 1996 Issued
Array ( [id] => 3765433 [patent_doc_number] => 05802568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers' [patent_app_type] => 1 [patent_app_number] => 8/660090 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3712 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802568.pdf [firstpage_image] =>[orig_patent_app_number] => 660090 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660090
Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers Jun 5, 1996 Issued
Array ( [id] => 3833551 [patent_doc_number] => 05813041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Method for accessing memory by activating a programmable chip select signal' [patent_app_type] => 1 [patent_app_number] => 8/660028 [patent_app_country] => US [patent_app_date] => 1996-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/813/05813041.pdf [firstpage_image] =>[orig_patent_app_number] => 660028 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660028
Method for accessing memory by activating a programmable chip select signal Jun 5, 1996 Issued
Array ( [id] => 4200112 [patent_doc_number] => 06021480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line' [patent_app_type] => 1 [patent_app_number] => 8/658752 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 127 [patent_figures_cnt] => 135 [patent_no_of_words] => 71019 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021480.pdf [firstpage_image] =>[orig_patent_app_number] => 658752 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658752
Aligning a memory read request with a cache line boundary when the request is for data beginning at a location in the middle of the cache line Jun 4, 1996 Issued
Array ( [id] => 3705881 [patent_doc_number] => 05651131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Refreshing a dynamic random access memory utilizing a mandatory or optional refresh' [patent_app_type] => 1 [patent_app_number] => 8/657533 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3434 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/651/05651131.pdf [firstpage_image] =>[orig_patent_app_number] => 657533 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657533
Refreshing a dynamic random access memory utilizing a mandatory or optional refresh Jun 4, 1996 Issued
Array ( [id] => 4020233 [patent_doc_number] => 05860143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Real-time image data access from virtual memory in a digital printing system' [patent_app_type] => 1 [patent_app_number] => 8/659969 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3727 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860143.pdf [firstpage_image] =>[orig_patent_app_number] => 659969 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/659969
Real-time image data access from virtual memory in a digital printing system Jun 2, 1996 Issued
Array ( [id] => 3996000 [patent_doc_number] => 05918244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method and system for coherently caching I/O devices across a network' [patent_app_type] => 1 [patent_app_number] => 8/657777 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 48 [patent_no_of_words] => 16165 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918244.pdf [firstpage_image] =>[orig_patent_app_number] => 657777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657777
Method and system for coherently caching I/O devices across a network May 30, 1996 Issued
Array ( [id] => 3765789 [patent_doc_number] => 05802592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'System and method for protecting integrity of alterable ROM using digital signatures' [patent_app_type] => 1 [patent_app_number] => 8/656626 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2952 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802592.pdf [firstpage_image] =>[orig_patent_app_number] => 656626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656626
System and method for protecting integrity of alterable ROM using digital signatures May 30, 1996 Issued
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