Search

Reginald Glenwood Bragdon

Supervisory Patent Examiner (ID: 2283, Phone: (571)272-4204 , Office: P/2139 )

Most Active Art Unit
2751
Art Unit(s)
2189, 2188, 2312, 2751, 2186, 2139, 2185, 2787
Total Applications
790
Issued Applications
531
Pending Applications
75
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3853195 [patent_doc_number] => 05761708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Apparatus and method to speculatively initiate primary memory accesses' [patent_app_type] => 1 [patent_app_number] => 8/658874 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3629 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761708.pdf [firstpage_image] =>[orig_patent_app_number] => 658874 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658874
Apparatus and method to speculatively initiate primary memory accesses May 30, 1996 Issued
Array ( [id] => 3765789 [patent_doc_number] => 05802592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'System and method for protecting integrity of alterable ROM using digital signatures' [patent_app_type] => 1 [patent_app_number] => 8/656626 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2952 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802592.pdf [firstpage_image] =>[orig_patent_app_number] => 656626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656626
System and method for protecting integrity of alterable ROM using digital signatures May 30, 1996 Issued
Array ( [id] => 3908335 [patent_doc_number] => 05778435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'History-based prefetch cache including a time queue' [patent_app_type] => 1 [patent_app_number] => 8/655590 [patent_app_country] => US [patent_app_date] => 1996-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4890 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778435.pdf [firstpage_image] =>[orig_patent_app_number] => 655590 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655590
History-based prefetch cache including a time queue May 29, 1996 Issued
Array ( [id] => 3944442 [patent_doc_number] => 05946716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Sectored virtual memory management system and translation look-aside buffer (TLB) for the same' [patent_app_type] => 1 [patent_app_number] => 8/656938 [patent_app_country] => US [patent_app_date] => 1996-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5882 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946716.pdf [firstpage_image] =>[orig_patent_app_number] => 656938 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656938
Sectored virtual memory management system and translation look-aside buffer (TLB) for the same May 29, 1996 Issued
Array ( [id] => 3800428 [patent_doc_number] => 05819310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Method and apparatus for reading data from mirrored logical volumes on physical disk drives' [patent_app_type] => 1 [patent_app_number] => 8/653154 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9181 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/819/05819310.pdf [firstpage_image] =>[orig_patent_app_number] => 653154 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653154
Method and apparatus for reading data from mirrored logical volumes on physical disk drives May 23, 1996 Issued
Array ( [id] => 3781976 [patent_doc_number] => 05845316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Scheduling random I/O for data storage tape' [patent_app_type] => 1 [patent_app_number] => 8/652880 [patent_app_country] => US [patent_app_date] => 1996-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 29 [patent_no_of_words] => 8314 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/845/05845316.pdf [firstpage_image] =>[orig_patent_app_number] => 652880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/652880
Scheduling random I/O for data storage tape May 22, 1996 Issued
Array ( [id] => 4060820 [patent_doc_number] => 05895481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Programmable VESA unified memory architecture (VUMA) row address strobe (RAS)' [patent_app_type] => 1 [patent_app_number] => 8/651370 [patent_app_country] => US [patent_app_date] => 1996-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4735 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895481.pdf [firstpage_image] =>[orig_patent_app_number] => 651370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/651370
Programmable VESA unified memory architecture (VUMA) row address strobe (RAS) May 21, 1996 Issued
Array ( [id] => 3917613 [patent_doc_number] => 05751936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Checking for proper locations of storage devices in a storage device array' [patent_app_type] => 1 [patent_app_number] => 8/645124 [patent_app_country] => US [patent_app_date] => 1996-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751936.pdf [firstpage_image] =>[orig_patent_app_number] => 645124 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/645124
Checking for proper locations of storage devices in a storage device array May 12, 1996 Issued
Array ( [id] => 4019272 [patent_doc_number] => 05860079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Arrangement and method for efficient calculation of memory addresses in a block storage memory system' [patent_app_type] => 1 [patent_app_number] => 8/644317 [patent_app_country] => US [patent_app_date] => 1996-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5171 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860079.pdf [firstpage_image] =>[orig_patent_app_number] => 644317 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644317
Arrangement and method for efficient calculation of memory addresses in a block storage memory system May 9, 1996 Issued
Array ( [id] => 4026744 [patent_doc_number] => 05890191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory' [patent_app_type] => 1 [patent_app_number] => 8/644098 [patent_app_country] => US [patent_app_date] => 1996-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5347 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890191.pdf [firstpage_image] =>[orig_patent_app_number] => 644098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644098
Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory May 9, 1996 Issued
Array ( [id] => 4001701 [patent_doc_number] => 05950219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same' [patent_app_type] => 1 [patent_app_number] => 8/641887 [patent_app_country] => US [patent_app_date] => 1996-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5773 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950219.pdf [firstpage_image] =>[orig_patent_app_number] => 641887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641887
Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same May 1, 1996 Issued
Array ( [id] => 3659893 [patent_doc_number] => 05630090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Apparatus for and methods of providing a safe-stop mode for a microprocessor operating in a PSRAM-memory environment' [patent_app_type] => 1 [patent_app_number] => 8/644607 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5323 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630090.pdf [firstpage_image] =>[orig_patent_app_number] => 644607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/644607
Apparatus for and methods of providing a safe-stop mode for a microprocessor operating in a PSRAM-memory environment Apr 25, 1996 Issued
Array ( [id] => 3808132 [patent_doc_number] => 05727182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Method and apparatus for adjusting output current values for expansion memories' [patent_app_type] => 1 [patent_app_number] => 8/637996 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4752 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727182.pdf [firstpage_image] =>[orig_patent_app_number] => 637996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/637996
Method and apparatus for adjusting output current values for expansion memories Apr 24, 1996 Issued
Array ( [id] => 3853153 [patent_doc_number] => 05761705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Methods and structure for maintaining cache consistency in a RAID controller having redundant caches' [patent_app_type] => 1 [patent_app_number] => 8/630906 [patent_app_country] => US [patent_app_date] => 1996-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7298 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761705.pdf [firstpage_image] =>[orig_patent_app_number] => 630906 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630906
Methods and structure for maintaining cache consistency in a RAID controller having redundant caches Apr 3, 1996 Issued
Array ( [id] => 3798031 [patent_doc_number] => 05809523 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'System and method for determining relative cache performance in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/627936 [patent_app_country] => US [patent_app_date] => 1996-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8209 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809523.pdf [firstpage_image] =>[orig_patent_app_number] => 627936 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627936
System and method for determining relative cache performance in a computer system Mar 27, 1996 Issued
Array ( [id] => 3805895 [patent_doc_number] => 05822772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Memory controller and method of memory access sequence recordering that eliminates page miss and row miss penalties' [patent_app_type] => 1 [patent_app_number] => 8/620592 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4314 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822772.pdf [firstpage_image] =>[orig_patent_app_number] => 620592 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620592
Memory controller and method of memory access sequence recordering that eliminates page miss and row miss penalties Mar 21, 1996 Issued
08/619959 METHOD AND APPARATUS FOR USING A DIRECT MEMORY ACCESS UNIT AND DATA CACHE UNIT IN A MICROPROCESSOR Mar 19, 1996 Abandoned
Array ( [id] => 4059385 [patent_doc_number] => 05875451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM' [patent_app_type] => 1 [patent_app_number] => 8/615392 [patent_app_country] => US [patent_app_date] => 1996-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5505 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875451.pdf [firstpage_image] =>[orig_patent_app_number] => 615392 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/615392
Computer hybrid memory including DRAM and EDRAM memory components, with secondary cache in EDRAM for DRAM Mar 13, 1996 Issued
Array ( [id] => 3871033 [patent_doc_number] => 05706464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method and system for achieving atomic memory references in a multilevel cache data processing system' [patent_app_type] => 1 [patent_app_number] => 8/608978 [patent_app_country] => US [patent_app_date] => 1996-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6251 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706464.pdf [firstpage_image] =>[orig_patent_app_number] => 608978 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608978
Method and system for achieving atomic memory references in a multilevel cache data processing system Feb 28, 1996 Issued
Array ( [id] => 3798535 [patent_doc_number] => 05809554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'User control of multiple memory heaps' [patent_app_type] => 1 [patent_app_number] => 8/559904 [patent_app_country] => US [patent_app_date] => 1996-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5752 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809554.pdf [firstpage_image] =>[orig_patent_app_number] => 559904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/559904
User control of multiple memory heaps Feb 25, 1996 Issued
Menu