Reginald Glenwood Bragdon

Array ( [id] => 3853345 [patent_doc_number] => 05761719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'On-chip memory map for processor cache macro' [patent_app_type] => 1 [patent_app_number] => 8/468885 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3365 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761719.pdf [firstpage_image] =>[orig_patent_app_number] => 468885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3681711 [patent_doc_number] => 05600815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'High density buffer memory architecture' [patent_app_type] => 1 [patent_app_number] => 8/469928 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 9689 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600815.pdf [firstpage_image] =>[orig_patent_app_number] => 469928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3808089 [patent_doc_number] => 05727179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Memory access method using intermediate addresses' [patent_app_type] => 1 [patent_app_number] => 8/466760 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3598 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/727/05727179.pdf [firstpage_image] =>[orig_patent_app_number] => 466760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3853207 [patent_doc_number] => 05761709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Write cache for servicing write requests within a predetermined address range' [patent_app_type] => 1 [patent_app_number] => 8/464352 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3871 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761709.pdf [firstpage_image] =>[orig_patent_app_number] => 464352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3751107 [patent_doc_number] => 05699548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Method and apparatus for selecting a mode for updating external memory' [patent_app_type] => 1 [patent_app_number] => 8/456716 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 8718 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699548.pdf [firstpage_image] =>[orig_patent_app_number] => 456716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3922894 [patent_doc_number] => 05752269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Pipelined microprocessor that pipelines memory requests to an external memory' [patent_app_type] => 1 [patent_app_number] => 8/451150 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3973 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752269.pdf [firstpage_image] =>[orig_patent_app_number] => 451150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3918593 [patent_doc_number] => 05751998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Memory accessing system with portions of memory being selectively write protectable and relocatable based on predefined register bits and memory selection RAM outputs' [patent_app_type] => 1 [patent_app_number] => 8/450548 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11184 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751998.pdf [firstpage_image] =>[orig_patent_app_number] => 450548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767335 [patent_doc_number] => 05721870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Lock control for a shared main storage data processing system' [patent_app_type] => 1 [patent_app_number] => 8/447026 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 5781 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721870.pdf [firstpage_image] =>[orig_patent_app_number] => 447026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3701181 [patent_doc_number] => 05664140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Processor to memory interface logic for use in a computer system using a multiplexed memory address' [patent_app_type] => 1 [patent_app_number] => 8/444750 [patent_app_country] => US [patent_app_date] => 1995-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3862 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664140.pdf [firstpage_image] =>[orig_patent_app_number] => 444750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3741765 [patent_doc_number] => 05671388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method and apparatus for performing write operations in multi-level cell storage device' [patent_app_type] => 1 [patent_app_number] => 8/433614 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671388.pdf [firstpage_image] =>[orig_patent_app_number] => 433614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3900957 [patent_doc_number] => 05806083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Apparatus and method for an improved content addressable memory using a random access memory to generate match information' [patent_app_type] => 1 [patent_app_number] => 8/431561 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6983 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/806/05806083.pdf [firstpage_image] =>[orig_patent_app_number] => 431561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3707850 [patent_doc_number] => 05680582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Method for heap coalescing where blocks do not cross page of segment boundaries' [patent_app_type] => 1 [patent_app_number] => 8/430446 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5890 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680582.pdf [firstpage_image] =>[orig_patent_app_number] => 430446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3700427 [patent_doc_number] => 05696937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Cache controller utilizing a state machine for controlling invalidations in a network with dual system busses' [patent_app_type] => 1 [patent_app_number] => 8/431366 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 12782 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696937.pdf [firstpage_image] =>[orig_patent_app_number] => 431366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4033659 [patent_doc_number] => 05963976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'System for configuring a duplex shared storage' [patent_app_type] => 1 [patent_app_number] => 8/426186 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 11356 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963976.pdf [firstpage_image] =>[orig_patent_app_number] => 426186 [rel_patent_id] =>[rel_patent_doc_number] =>)