| Application number | Title of the application | Filing Date | Status |
|---|
| 08/416489 | BUS OF CPU CORE OPTIMIZED FOR ACCESSING ON-CHIP MEMORY DEVICES | Apr 3, 1995 | Abandoned |
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[patent_app_number] => 8/416475
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| 08/423016 | CACHE COHERENT COMPUTER SYSTEM THAT MINIMIZES INVALIDATION AND COPYBACK OPERATIONS | Mar 30, 1995 | Abandoned |
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[patent_doc_number] => 05649155
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[patent_kind] => NA
[patent_issue_date] => 1997-07-15
[patent_title] => 'Cache memory accessed by continuation requests'
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| 08/414206 | TRANSLATION LOOK-ASIDE BUFFER INCLUDING A SINGLE PAGE SIZE TRANSLATION UNIT | Mar 30, 1995 | Abandoned |
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[patent_doc_number] => 05682513
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[patent_doc_number] => 05524229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
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| 08/397066 | PROCESS AND SYSTEM FOR SWITCHING BETWEEN AN UPDATE AND INVALIDATE MODE FOR EACH CACHE BLOCK | Mar 14, 1995 | Abandoned |
| 08/398428 | PREDICTIVE CACHING SYSTEM AND METHOD BASED ON MEMORY ACCESS WHICH PREVIOUSLY FOLLOWED A CACHE MISS | Mar 5, 1995 | Abandoned |
Array
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Array
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[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Method for processing data by utilizing hierarchical cache memories and processing system with the hierarchiacal cache memories'
[patent_app_type] => 1
[patent_app_number] => 8/396899
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Array
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[patent_kind] => NA
[patent_issue_date] => 1997-06-10
[patent_title] => 'Variable refresh intervals for system devices including setting the refresh interval to zero'
[patent_app_type] => 1
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Array
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[patent_kind] => NA
[patent_issue_date] => 1997-06-17
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Array
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[id] => 3901095
[patent_doc_number] => 05715426
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Set-associative cache memory with shared sense amplifiers'
[patent_app_type] => 1
[patent_app_number] => 8/386130
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/386130 | Set-associative cache memory with shared sense amplifiers | Feb 8, 1995 | Issued |
| 08/385197 | OPTIONAL REFRESH | Feb 6, 1995 | Abandoned |
| 08/407641 | A SYSTEM FOR ALLOCATING AND ACCESSING SHARED STORAGE USING PROGRAM MODE AND DMA MODE | Jan 31, 1995 | Abandoned |
Array
(
[id] => 3745254
[patent_doc_number] => 05694570
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Method and system of buffering data written to direct access storage devices in data processing systems'
[patent_app_type] => 1
[patent_app_number] => 8/376292
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| 08/375846 | HYBRID TAG ARCHITECTURE FOR A CACHE MEMORY | Jan 19, 1995 | Abandoned |
| 08/376124 | METHOD AND APPARATUS FOR A COHERENT COPY-BACK BUFFER IN A MULTIPROCESSOR COMPUTER SYSTEM | Jan 18, 1995 | Abandoned |
