Reginald Glenwood Bragdon

Array ( [id] => 3709015 [patent_doc_number] => 05678025 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Cache coherency maintenance of non-cache supporting buses' [patent_app_type] => 1 [patent_app_number] => 8/373892 [patent_app_country] => US [patent_app_date] => 1995-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5562 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/678/05678025.pdf [firstpage_image] =>[orig_patent_app_number] => 373892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3730565 [patent_doc_number] => 05617554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Physical address size selection and page size selection in an address translator' [patent_app_type] => 1 [patent_app_number] => 8/372805 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7554 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617554.pdf [firstpage_image] =>[orig_patent_app_number] => 372805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3794312 [patent_doc_number] => 05809278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Circuit for controlling access to a common memory based on priority' [patent_app_type] => 1 [patent_app_number] => 8/363528 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 11199 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/809/05809278.pdf [firstpage_image] =>[orig_patent_app_number] => 363528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3534144 [patent_doc_number] => 05530958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Cache memory system and method with multiple hashing functions and hash control storage' [patent_app_type] => 1 [patent_app_number] => 8/363542 [patent_app_country] => US [patent_app_date] => 1994-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8658 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530958.pdf [firstpage_image] =>[orig_patent_app_number] => 363542 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3659907 [patent_doc_number] => 05630091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'High density buffer architecture and method' [patent_app_type] => 1 [patent_app_number] => 8/357166 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 9681 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630091.pdf [firstpage_image] =>[orig_patent_app_number] => 357166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3671128 [patent_doc_number] => 05627986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Device and method for selecting and addressing extended memory addresses' [patent_app_type] => 1 [patent_app_number] => 8/352296 [patent_app_country] => US [patent_app_date] => 1994-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3730 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627986.pdf [firstpage_image] =>[orig_patent_app_number] => 352296 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3636669 [patent_doc_number] => 05603011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Selective shadowing and paging in computer memory systems' [patent_app_type] => 1 [patent_app_number] => 8/342402 [patent_app_country] => US [patent_app_date] => 1994-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8665 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603011.pdf [firstpage_image] =>[orig_patent_app_number] => 342402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3600067 [patent_doc_number] => 05553258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Method and apparatus for forming an exchange address for a system with different size caches' [patent_app_type] => 1 [patent_app_number] => 8/340125 [patent_app_country] => US [patent_app_date] => 1994-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 40059 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553258.pdf [firstpage_image] =>[orig_patent_app_number] => 340125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3636620 [patent_doc_number] => 05603008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Computer system having cache memories with independently validated keys in the TLB' [patent_app_type] => 1 [patent_app_number] => 8/337133 [patent_app_country] => US [patent_app_date] => 1994-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6329 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 402 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/603/05603008.pdf [firstpage_image] =>[orig_patent_app_number] => 337133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3676384 [patent_doc_number] => 05598528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Checking for proper locations of storage device in a storage device array' [patent_app_type] => 1 [patent_app_number] => 8/325989 [patent_app_country] => US [patent_app_date] => 1994-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6487 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598528.pdf [firstpage_image] =>[orig_patent_app_number] => 325989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3708958 [patent_doc_number] => 05678021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Apparatus and method for a memory unit with a processor integrated therein' [patent_app_type] => 1 [patent_app_number] => 8/324291 [patent_app_country] => US [patent_app_date] => 1994-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3871 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/678/05678021.pdf [firstpage_image] =>[orig_patent_app_number] => 324291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122529 [patent_doc_number] => 05465337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-07 [patent_title] => 'Method and apparatus for a memory management unit supporting multiple page sizes' [patent_app_type] => 1 [patent_app_number] => 8/318539 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5902 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/465/05465337.pdf [firstpage_image] =>[orig_patent_app_number] => 318539 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3707644 [patent_doc_number] => 05680570 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Memory system with dynamically allocatable non-volatile storage capability' [patent_app_type] => 1 [patent_app_number] => 8/316057 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6056 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680570.pdf [firstpage_image] =>[orig_patent_app_number] => 316057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3741851 [patent_doc_number] => 05671394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Microcomputer having ROM data protection function' [patent_app_type] => 1 [patent_app_number] => 8/313534 [patent_app_country] => US [patent_app_date] => 1994-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3757 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671394.pdf [firstpage_image] =>[orig_patent_app_number] => 313534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3595610 [patent_doc_number] => 05581722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Memory management unit for managing address operations corresponding to domains using environmental control' [patent_app_type] => 1 [patent_app_number] => 8/311911 [patent_app_country] => US [patent_app_date] => 1994-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581722.pdf [firstpage_image] =>[orig_patent_app_number] => 311911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3534078 [patent_doc_number] => 05530955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Page memory device capable of short cycle access of different pages by a plurality of data processors' [patent_app_type] => 1 [patent_app_number] => 8/308527 [patent_app_country] => US [patent_app_date] => 1994-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8715 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530955.pdf [firstpage_image] =>[orig_patent_app_number] => 308527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3592951 [patent_doc_number] => 05499383 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'DMA control device controlling sequential storage of data' [patent_app_type] => 1 [patent_app_number] => 8/301222 [patent_app_country] => US [patent_app_date] => 1994-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2986 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499383.pdf [firstpage_image] =>[orig_patent_app_number] => 301222 [rel_patent_id] =>[rel_patent_doc_number] =>)