Search

Reginald Glenwood Bragdon

Examiner (ID: 2350)

Most Active Art Unit
2751
Art Unit(s)
2751, 2188, 2189, 2186, 2787, 2312, 2185, 2139
Total Applications
790
Issued Applications
531
Pending Applications
74
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
08/297696 IDENTIFICATION OF THE DISTINCTION BETWEEN THE BEGINNING OF A NEW WRITE BACK CYCLE AND ONGOING WRITE CYCLE Aug 28, 1994 Abandoned
Array ( [id] => 3605856 [patent_doc_number] => 05522055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Electronic file system with pre read memory management of data to be displayed' [patent_app_type] => 1 [patent_app_number] => 8/295488 [patent_app_country] => US [patent_app_date] => 1994-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 46 [patent_no_of_words] => 15748 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/522/05522055.pdf [firstpage_image] =>[orig_patent_app_number] => 295488 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/295488
Electronic file system with pre read memory management of data to be displayed Aug 24, 1994 Issued
Array ( [id] => 3434932 [patent_doc_number] => 05459839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'System and method for managing queue read and write pointers' [patent_app_type] => 1 [patent_app_number] => 8/293930 [patent_app_country] => US [patent_app_date] => 1994-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 27356 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459839.pdf [firstpage_image] =>[orig_patent_app_number] => 293930 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/293930
System and method for managing queue read and write pointers Aug 21, 1994 Issued
Array ( [id] => 3117856 [patent_doc_number] => 05448714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Sequential-access and random-access dual-port memory buffer' [patent_app_type] => 1 [patent_app_number] => 8/293116 [patent_app_country] => US [patent_app_date] => 1994-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4476 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 551 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448714.pdf [firstpage_image] =>[orig_patent_app_number] => 293116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/293116
Sequential-access and random-access dual-port memory buffer Aug 18, 1994 Issued
Array ( [id] => 3600209 [patent_doc_number] => 05497480 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-05 [patent_title] => 'Broadcast demap for deallocating memory pages in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/282170 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2052 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/497/05497480.pdf [firstpage_image] =>[orig_patent_app_number] => 282170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282170
Broadcast demap for deallocating memory pages in a multiprocessor system Jul 28, 1994 Issued
Array ( [id] => 3440894 [patent_doc_number] => 05463755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'High-performance, multi-bank global memory card for multiprocessor systems' [patent_app_type] => 1 [patent_app_number] => 8/263746 [patent_app_country] => US [patent_app_date] => 1994-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10394 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463755.pdf [firstpage_image] =>[orig_patent_app_number] => 263746 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/263746
High-performance, multi-bank global memory card for multiprocessor systems Jun 21, 1994 Issued
08/252632 ON-CHIP MEMORY MAP FOR PROCESSOR CACHE MACRO Jun 1, 1994 Abandoned
08/252053 HIGH PERFORMANCE PROCESSOR BUS PROTOCOL HAVING INTERLEAVED CACHE ACCESSES DURING EXTERNAL FETCH OF MISSED CACHE LINES May 31, 1994 Abandoned
Array ( [id] => 3007532 [patent_doc_number] => 05367660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Line buffer for cache memory' [patent_app_type] => 1 [patent_app_number] => 8/241328 [patent_app_country] => US [patent_app_date] => 1994-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 8528 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367660.pdf [firstpage_image] =>[orig_patent_app_number] => 241328 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/241328
Line buffer for cache memory May 10, 1994 Issued
Array ( [id] => 3741704 [patent_doc_number] => 05671385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Memory subsystem with disk meshing, controller meshing, and efficient cache buffer lookup' [patent_app_type] => 1 [patent_app_number] => 8/235714 [patent_app_country] => US [patent_app_date] => 1994-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 13603 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671385.pdf [firstpage_image] =>[orig_patent_app_number] => 235714 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/235714
Memory subsystem with disk meshing, controller meshing, and efficient cache buffer lookup Apr 28, 1994 Issued
Array ( [id] => 4071536 [patent_doc_number] => 05933844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Write through virtual cache memory, alias addressing, and cache flushes' [patent_app_type] => 1 [patent_app_number] => 8/232600 [patent_app_country] => US [patent_app_date] => 1994-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2917 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933844.pdf [firstpage_image] =>[orig_patent_app_number] => 232600 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/232600
Write through virtual cache memory, alias addressing, and cache flushes Apr 24, 1994 Issued
Array ( [id] => 3600126 [patent_doc_number] => 05553262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Memory apparatus and method capable of setting attribute of information to be cached' [patent_app_type] => 1 [patent_app_number] => 8/231963 [patent_app_country] => US [patent_app_date] => 1994-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 11256 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/553/05553262.pdf [firstpage_image] =>[orig_patent_app_number] => 231963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/231963
Memory apparatus and method capable of setting attribute of information to be cached Apr 21, 1994 Issued
08/230117 MEMORY CONTROL DEVICE AND MEMORY DATA SEARCH CIRCUIT Apr 19, 1994 Abandoned
Array ( [id] => 3824901 [patent_doc_number] => 05710904 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Microprocessor having address pre-outputting function and data processor using the same' [patent_app_type] => 1 [patent_app_number] => 8/225870 [patent_app_country] => US [patent_app_date] => 1994-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 28122 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710904.pdf [firstpage_image] =>[orig_patent_app_number] => 225870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/225870
Microprocessor having address pre-outputting function and data processor using the same Apr 10, 1994 Issued
Array ( [id] => 3563091 [patent_doc_number] => 05548786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Dynamic bus sizing of DMA transfers' [patent_app_type] => 1 [patent_app_number] => 8/224123 [patent_app_country] => US [patent_app_date] => 1994-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10510 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548786.pdf [firstpage_image] =>[orig_patent_app_number] => 224123 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/224123
Dynamic bus sizing of DMA transfers Apr 5, 1994 Issued
Array ( [id] => 3474313 [patent_doc_number] => 05469560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Prioritizing pending read requests in an automated storage library' [patent_app_type] => 1 [patent_app_number] => 8/224089 [patent_app_country] => US [patent_app_date] => 1994-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5051 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469560.pdf [firstpage_image] =>[orig_patent_app_number] => 224089 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/224089
Prioritizing pending read requests in an automated storage library Apr 4, 1994 Issued
08/177675 APPARATUS FOR PROVIDING A SAFE-STOP MODE FOR A MICROPROCESSOR OPERATING IN A PSRAM-MEMORY ENVIRONMENT Jan 4, 1994 Abandoned
Array ( [id] => 3681783 [patent_doc_number] => 05600820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Method for partitioning memory in a high speed network based on the type of service' [patent_app_type] => 1 [patent_app_number] => 8/160525 [patent_app_country] => US [patent_app_date] => 1993-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5190 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600820.pdf [firstpage_image] =>[orig_patent_app_number] => 160525 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/160525
Method for partitioning memory in a high speed network based on the type of service Nov 30, 1993 Issued
Array ( [id] => 3765404 [patent_doc_number] => 05802566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Method and system for predicting addresses and prefetching data into a cache memory' [patent_app_type] => 1 [patent_app_number] => 8/140097 [patent_app_country] => US [patent_app_date] => 1993-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4588 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802566.pdf [firstpage_image] =>[orig_patent_app_number] => 140097 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/140097
Method and system for predicting addresses and prefetching data into a cache memory Nov 15, 1993 Issued
Array ( [id] => 3579540 [patent_doc_number] => 05485595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Flash memory mass storage architecture incorporating wear leveling technique without using cam cells' [patent_app_type] => 1 [patent_app_number] => 8/131495 [patent_app_country] => US [patent_app_date] => 1993-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8900 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485595.pdf [firstpage_image] =>[orig_patent_app_number] => 131495 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/131495
Flash memory mass storage architecture incorporating wear leveling technique without using cam cells Oct 3, 1993 Issued
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