
Rehana Perveen
Supervisory Patent Examiner (ID: 10862, Phone: (571)272-3676 , Office: P/2155 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2116, 2317, 2782, 2129, 2751, 2182, 2155, 2189, 2148 |
| Total Applications | 712 |
| Issued Applications | 630 |
| Pending Applications | 37 |
| Abandoned Applications | 47 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6085406
[patent_doc_number] => 20020083226
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-27
[patent_title] => 'Configuring computer components'
[patent_app_type] => new
[patent_app_number] => 09/750238
[patent_app_country] => US
[patent_app_date] => 2000-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2558
[patent_no_of_claims] => 30
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0083/20020083226.pdf
[firstpage_image] =>[orig_patent_app_number] => 09750238
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/750238 | Configuring computer components | Dec 26, 2000 | Issued |
Array
(
[id] => 6085451
[patent_doc_number] => 20020083247
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-27
[patent_title] => 'Relaxed read completion ordering in a system using transaction order queue'
[patent_app_type] => new
[patent_app_number] => 09/749111
[patent_app_country] => US
[patent_app_date] => 2000-12-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0083/20020083247.pdf
[firstpage_image] =>[orig_patent_app_number] => 09749111
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/749111 | Relaxed read completion ordering in a system using transaction order queue | Dec 25, 2000 | Issued |
Array
(
[id] => 6894517
[patent_doc_number] => 20010016883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-23
[patent_title] => 'Data transfer apparatus'
[patent_app_type] => new
[patent_app_number] => 09/747685
[patent_app_country] => US
[patent_app_date] => 2000-12-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0016/20010016883.pdf
[firstpage_image] =>[orig_patent_app_number] => 09747685
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/747685 | Data transfer apparatus | Dec 25, 2000 | Issued |
Array
(
[id] => 6656105
[patent_doc_number] => 20030009610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'Appliance sensor and man machine interface bus'
[patent_app_type] => new
[patent_app_number] => 09/742549
[patent_app_country] => US
[patent_app_date] => 2000-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 6144
[patent_no_of_claims] => 33
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[pdf_file] => publications/A1/0009/20030009610.pdf
[firstpage_image] =>[orig_patent_app_number] => 09742549
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/742549 | Appliance sensor and man machine interface bus | Dec 21, 2000 | Issued |
Array
(
[id] => 6134044
[patent_doc_number] => 20020078318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Programming network interface cards to perform system and network management functions'
[patent_app_type] => new
[patent_app_number] => 09/738581
[patent_app_country] => US
[patent_app_date] => 2000-12-18
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[pdf_file] => publications/A1/0078/20020078318.pdf
[firstpage_image] =>[orig_patent_app_number] => 09738581
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/738581 | Programming network interface cards to perform system and network management functions | Dec 17, 2000 | Issued |
Array
(
[id] => 1248775
[patent_doc_number] => 06678757
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-13
[patent_title] => 'Print data management system and method'
[patent_app_type] => B1
[patent_app_number] => 09/646420
[patent_app_country] => US
[patent_app_date] => 2000-12-12
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[pdf_file] => patents/06/678/06678757.pdf
[firstpage_image] =>[orig_patent_app_number] => 09646420
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/646420 | Print data management system and method | Dec 11, 2000 | Issued |
Array
(
[id] => 1415320
[patent_doc_number] => 06549960
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address'
[patent_app_type] => B1
[patent_app_number] => 09/714643
[patent_app_country] => US
[patent_app_date] => 2000-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[pdf_file] => patents/06/549/06549960.pdf
[firstpage_image] =>[orig_patent_app_number] => 09714643
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/714643 | Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address | Nov 15, 2000 | Issued |
Array
(
[id] => 1602171
[patent_doc_number] => 06493773
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-10
[patent_title] => 'Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems'
[patent_app_type] => B1
[patent_app_number] => 09/713998
[patent_app_country] => US
[patent_app_date] => 2000-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 5433
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/493/06493773.pdf
[firstpage_image] =>[orig_patent_app_number] => 09713998
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/713998 | Data validity measure for efficient implementation of first-in-first-out memories for multi-processor systems | Nov 14, 2000 | Issued |
| 09/601809 | Computer adapter card | Oct 3, 2000 | Abandoned |
Array
(
[id] => 1062196
[patent_doc_number] => 06854021
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-08
[patent_title] => 'Communications between partitions within a logically partitioned computer'
[patent_app_type] => utility
[patent_app_number] => 09/677454
[patent_app_country] => US
[patent_app_date] => 2000-10-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/854/06854021.pdf
[firstpage_image] =>[orig_patent_app_number] => 09677454
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/677454 | Communications between partitions within a logically partitioned computer | Oct 1, 2000 | Issued |
| 09/677423 | Wireless JAVA device | Oct 1, 2000 | Abandoned |
Array
(
[id] => 1456638
[patent_doc_number] => 06457076
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'System and method for modifying software residing on a client computer that has access to a network'
[patent_app_type] => B1
[patent_app_number] => 09/661117
[patent_app_country] => US
[patent_app_date] => 2000-09-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/661117 | System and method for modifying software residing on a client computer that has access to a network | Sep 12, 2000 | Issued |
Array
(
[id] => 1539990
[patent_doc_number] => 06338104
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[patent_issue_date] => 2002-01-08
[patent_title] => 'System including single connector pin supporter having two separate plurality of connector pins with one set of pins contacting state designating portion of memory card indicating write prohibit state'
[patent_app_type] => B1
[patent_app_number] => 09/658189
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/658189 | System including single connector pin supporter having two separate plurality of connector pins with one set of pins contacting state designating portion of memory card indicating write prohibit state | Sep 7, 2000 | Issued |
Array
(
[id] => 1408830
[patent_doc_number] => 06557047
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[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'External storage device and method of accessing same'
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Array
(
[id] => 1394864
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[patent_issue_date] => 2003-05-20
[patent_title] => 'Programmable controller coupler'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/601320 | Programmable controller coupler | Aug 6, 2000 | Issued |
Array
(
[id] => 1116528
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[patent_issue_date] => 2004-10-12
[patent_title] => 'Method and apparatus for controlling electrical devices in response to sensed conditions'
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Array
(
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[patent_title] => 'System for communicating status via first signal line in a period of time in which control signal via second line is not transmitted'
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[patent_app_number] => 09/626281
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Array
(
[id] => 1521631
[patent_doc_number] => 06502145
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[patent_issue_date] => 2002-12-31
[patent_title] => 'Semiconductor memory with application of predetermined power line potentials'
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[patent_app_number] => 09/609934
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/609934 | Semiconductor memory with application of predetermined power line potentials | Jun 29, 2000 | Issued |
Array
(
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[patent_title] => 'Dynamic message interface'
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Array
(
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[patent_title] => 'Speed power efficient USB method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/590831 | Speed power efficient USB method | Jun 8, 2000 | Issued |