Rei Tsang Shiao
Examiner (ID: 6494, Phone: (571)272-0707 , Office: P/1628 )
Most Active Art Unit | 1628 |
Art Unit(s) | 1628, 1626, 1629 |
Total Applications | 2891 |
Issued Applications | 2072 |
Pending Applications | 163 |
Abandoned Applications | 656 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7247298
[patent_doc_number] => 20040158788
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Method for functional verification of an integrated circuit model in order to create a verification platform, equipment emulator and verification platform'
[patent_app_type] => new
[patent_app_number] => 10/627976
[patent_app_country] => US
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[pdf_file] => publications/A1/0158/20040158788.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/627976 | Method for functional verification of an integrated circuit model in order to create a verification platform, equipment emulator and verification platform | Jul 27, 2003 | Abandoned |
Array
(
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[patent_doc_number] => 20040059977
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[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Method of processing test patterns for an integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/622933
[patent_app_country] => US
[patent_app_date] => 2003-07-18
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622933 | Method of processing test patterns for an integrated circuit | Jul 17, 2003 | Abandoned |
Array
(
[id] => 125930
[patent_doc_number] => 07711535
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-05-04
[patent_title] => 'Simulation of hardware and software'
[patent_app_type] => utility
[patent_app_number] => 10/618284
[patent_app_country] => US
[patent_app_date] => 2003-07-11
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/618284 | Simulation of hardware and software | Jul 10, 2003 | Issued |
Array
(
[id] => 7413593
[patent_doc_number] => 20040025127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-05
[patent_title] => 'Logic verification and logic cone extraction technique'
[patent_app_type] => new
[patent_app_number] => 10/612193
[patent_app_country] => US
[patent_app_date] => 2003-07-03
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/612193 | Logic verification and logic cone extraction technique | Jul 2, 2003 | Issued |
Array
(
[id] => 136795
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[patent_issue_date] => 2010-04-13
[patent_title] => 'System and method for dynamically allocating resources in a client/server environment'
[patent_app_type] => utility
[patent_app_number] => 10/611437
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/611437 | System and method for dynamically allocating resources in a client/server environment | Jun 29, 2003 | Issued |
Array
(
[id] => 7292648
[patent_doc_number] => 20040111252
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[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Method and system for emulating a design under test associated with a test environment'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/603776 | Method and system for emulating a design under test associated with a test environment | Jun 25, 2003 | Abandoned |
Array
(
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[patent_issue_date] => 2005-10-06
[patent_title] => 'Device comprising a communications stack with a scheduler'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2003-05-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/515657 | Device comprising a communications stack with a scheduler | May 26, 2003 | Abandoned |
Array
(
[id] => 7390835
[patent_doc_number] => 20040030417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-12
[patent_title] => 'Tracking systems for detecting sensor errors'
[patent_app_type] => new
[patent_app_number] => 10/416106
[patent_app_country] => US
[patent_app_date] => 2003-05-06
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[firstpage_image] =>[orig_patent_app_number] => 10416106
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/416106 | Tracking systems for detecting sensor errors | May 5, 2003 | Abandoned |
Array
(
[id] => 7320420
[patent_doc_number] => 20040225489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-11
[patent_title] => 'Integrated self-testing of a reconfigurable interconnect'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/428917 | Integrated self-testing of a reconfigurable interconnect | May 4, 2003 | Abandoned |
Array
(
[id] => 117077
[patent_doc_number] => 07716024
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Method and apparatus for electronically generating a color dental occlusion map within electronic model images'
[patent_app_type] => utility
[patent_app_number] => 10/426252
[patent_app_country] => US
[patent_app_date] => 2003-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => patents/07/716/07716024.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/426252 | Method and apparatus for electronically generating a color dental occlusion map within electronic model images | Apr 28, 2003 | Issued |
Array
(
[id] => 6726033
[patent_doc_number] => 20030208345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-06
[patent_title] => 'Color matching and simulation of multicolor surfaces'
[patent_app_type] => new
[patent_app_number] => 10/423441
[patent_app_country] => US
[patent_app_date] => 2003-04-25
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[pdf_file] => publications/A1/0208/20030208345.pdf
[firstpage_image] =>[orig_patent_app_number] => 10423441
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/423441 | Color matching and simulation of multicolor surfaces | Apr 24, 2003 | Abandoned |
Array
(
[id] => 155768
[patent_doc_number] => 07680637
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-03-16
[patent_title] => 'Automated linearization analysis'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/414645 | Automated linearization analysis | Apr 15, 2003 | Issued |
Array
(
[id] => 7351887
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[patent_title] => 'Systems, methods, and apparatus for automated dimensional model definitions and builds utilizing simplified analysis heuristics'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/402026 | Systems, methods, and apparatus for automated dimensional model definitions and builds utilizing simplified analysis heuristics | Mar 27, 2003 | Abandoned |
Array
(
[id] => 7350741
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[patent_title] => 'Method for CPU simulation using virtual machine extensions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395557 | Method for CPU simulation using virtual machine extensions | Mar 23, 2003 | Abandoned |
Array
(
[id] => 361966
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/326679 | Method and system for modeling distributed time invariant systems | Dec 19, 2002 | Issued |
Array
(
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[patent_title] => 'Method and apparatus for manipulating data of a disc media'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313093 | Method and apparatus for manipulating data of a disc media | Dec 4, 2002 | Abandoned |
Array
(
[id] => 4972544
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[patent_title] => 'Method and system for integrated reservoir and surface facility networks simulations'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/301788 | Integration of a discrete event simulation with a configurable software application | Nov 21, 2002 | Abandoned |