
Remmon R. Forde
Examiner (ID: 12393)
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826, 2812, 2852, 2813 |
| Total Applications | 309 |
| Issued Applications | 275 |
| Pending Applications | 5 |
| Abandoned Applications | 29 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 963955
[patent_doc_number] => 06949768
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-27
[patent_title] => 'Planar substrate devices integrated with finfets and method of manufacture'
[patent_app_type] => utility
[patent_app_number] => 10/711974
[patent_app_country] => US
[patent_app_date] => 2004-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 4251
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949768.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711974
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711974 | Planar substrate devices integrated with finfets and method of manufacture | Oct 17, 2004 | Issued |
Array
(
[id] => 963983
[patent_doc_number] => 06949796
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-27
[patent_title] => 'Halo implant in semiconductor structures'
[patent_app_type] => utility
[patent_app_number] => 10/711484
[patent_app_country] => US
[patent_app_date] => 2004-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 4612
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949796.pdf
[firstpage_image] =>[orig_patent_app_number] => 10711484
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/711484 | Halo implant in semiconductor structures | Sep 20, 2004 | Issued |
Array
(
[id] => 1018648
[patent_doc_number] => 06891230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-10
[patent_title] => 'Bipolar ESD protection structure'
[patent_app_type] => utility
[patent_app_number] => 10/790925
[patent_app_country] => US
[patent_app_date] => 2004-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 2951
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/891/06891230.pdf
[firstpage_image] =>[orig_patent_app_number] => 10790925
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/790925 | Bipolar ESD protection structure | Mar 1, 2004 | Issued |
Array
(
[id] => 7616726
[patent_doc_number] => 06946716
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-20
[patent_title] => 'Electroplated interconnection structures on integrated circuit chips'
[patent_app_type] => utility
[patent_app_number] => 10/773434
[patent_app_country] => US
[patent_app_date] => 2004-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 42
[patent_no_of_words] => 5679
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/946/06946716.pdf
[firstpage_image] =>[orig_patent_app_number] => 10773434
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/773434 | Electroplated interconnection structures on integrated circuit chips | Feb 8, 2004 | Issued |
Array
(
[id] => 7234439
[patent_doc_number] => 20040256629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Opto-electronic component with radiation-transmissive electrical contact layer'
[patent_app_type] => new
[patent_app_number] => 10/749433
[patent_app_country] => US
[patent_app_date] => 2003-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 1905
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20040256629.pdf
[firstpage_image] =>[orig_patent_app_number] => 10749433
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/749433 | Opto-electronic component with radiation-transmissive electrical contact layer | Dec 30, 2003 | Issued |
Array
(
[id] => 7191317
[patent_doc_number] => 20050040464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'SOI TYPE MOSFET'
[patent_app_type] => utility
[patent_app_number] => 10/730094
[patent_app_country] => US
[patent_app_date] => 2003-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 5425
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[pdf_file] => publications/A1/0040/20050040464.pdf
[firstpage_image] =>[orig_patent_app_number] => 10730094
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/730094 | SOI type MOSFET | Dec 8, 2003 | Issued |
Array
(
[id] => 7169150
[patent_doc_number] => 20050121746
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'HIGH PERFORMANCE DIODE IMPLANTED VOLTAGE CONTROLLED P-TYPE DIFFUSION RESISTOR'
[patent_app_type] => utility
[patent_app_number] => 10/730554
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2780
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20050121746.pdf
[firstpage_image] =>[orig_patent_app_number] => 10730554
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/730554 | High performance diode implanted voltage controlled p-type diffusion resistor | Dec 7, 2003 | Issued |
Array
(
[id] => 7286423
[patent_doc_number] => 20040108546
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'MOS transistor and fabrication method thereof'
[patent_app_type] => new
[patent_app_number] => 10/725383
[patent_app_country] => US
[patent_app_date] => 2003-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2291
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20040108546.pdf
[firstpage_image] =>[orig_patent_app_number] => 10725383
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725383 | MOS transistor and fabrication method thereof | Dec 2, 2003 | Issued |
Array
(
[id] => 7221984
[patent_doc_number] => 20040155692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Power device with bi-directional level shift circuit'
[patent_app_type] => new
[patent_app_number] => 10/726335
[patent_app_country] => US
[patent_app_date] => 2003-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 7721
[patent_no_of_claims] => 14
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[pdf_file] => publications/A1/0155/20040155692.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726335
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726335 | Power device with bi-directional level shift circuit | Nov 30, 2003 | Issued |
Array
(
[id] => 956502
[patent_doc_number] => 06956254
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-18
[patent_title] => 'Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing'
[patent_app_type] => utility
[patent_app_number] => 10/725234
[patent_app_country] => US
[patent_app_date] => 2003-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3169
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/956/06956254.pdf
[firstpage_image] =>[orig_patent_app_number] => 10725234
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/725234 | Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing | Nov 30, 2003 | Issued |
Array
(
[id] => 963611
[patent_doc_number] => 06949423
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-27
[patent_title] => 'MOSFET-fused nonvolatile read-only memory cell (MOFROM)'
[patent_app_type] => utility
[patent_app_number] => 10/723004
[patent_app_country] => US
[patent_app_date] => 2003-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 20
[patent_no_of_words] => 5010
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949423.pdf
[firstpage_image] =>[orig_patent_app_number] => 10723004
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/723004 | MOSFET-fused nonvolatile read-only memory cell (MOFROM) | Nov 25, 2003 | Issued |
Array
(
[id] => 7295969
[patent_doc_number] => 20040124518
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Semiconductor stacked multi-package module having inverted second package and electrically shielded first package'
[patent_app_type] => new
[patent_app_number] => 10/681833
[patent_app_country] => US
[patent_app_date] => 2003-10-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0124/20040124518.pdf
[firstpage_image] =>[orig_patent_app_number] => 10681833
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/681833 | Semiconductor stacked multi-package module having inverted second package and electrically shielded first package | Oct 7, 2003 | Issued |
Array
(
[id] => 1086529
[patent_doc_number] => 06831350
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-14
[patent_title] => 'Semiconductor structure with different lattice constant materials and method for forming the same'
[patent_app_type] => B1
[patent_app_number] => 10/677844
[patent_app_country] => US
[patent_app_date] => 2003-10-02
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/831/06831350.pdf
[firstpage_image] =>[orig_patent_app_number] => 10677844
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677844 | Semiconductor structure with different lattice constant materials and method for forming the same | Oct 1, 2003 | Issued |
Array
(
[id] => 7612451
[patent_doc_number] => 06903385
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-07
[patent_title] => 'Semiconductor structure having a textured nitride-based layer'
[patent_app_type] => utility
[patent_app_number] => 10/676963
[patent_app_country] => US
[patent_app_date] => 2003-10-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/903/06903385.pdf
[firstpage_image] =>[orig_patent_app_number] => 10676963
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676963 | Semiconductor structure having a textured nitride-based layer | Sep 30, 2003 | Issued |
Array
(
[id] => 985798
[patent_doc_number] => 06924531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-02
[patent_title] => 'LDMOS device with isolation guard rings'
[patent_app_type] => utility
[patent_app_number] => 10/676703
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10676703
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/676703 | LDMOS device with isolation guard rings | Sep 30, 2003 | Issued |
Array
(
[id] => 1095887
[patent_doc_number] => 06821826
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-23
[patent_title] => 'Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers'
[patent_app_type] => B1
[patent_app_number] => 10/674644
[patent_app_country] => US
[patent_app_date] => 2003-09-30
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[pdf_file] => patents/06/821/06821826.pdf
[firstpage_image] =>[orig_patent_app_number] => 10674644
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/674644 | Three dimensional CMOS integrated circuits having device layers built on different crystal oriented wafers | Sep 29, 2003 | Issued |
Array
(
[id] => 1116899
[patent_doc_number] => 06800897
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-10-05
[patent_title] => 'Integrated circuit power devices having junction barrier controlled schottky diodes therein'
[patent_app_type] => B2
[patent_app_number] => 10/671333
[patent_app_country] => US
[patent_app_date] => 2003-09-24
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[pdf_file] => patents/06/800/06800897.pdf
[firstpage_image] =>[orig_patent_app_number] => 10671333
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/671333 | Integrated circuit power devices having junction barrier controlled schottky diodes therein | Sep 23, 2003 | Issued |
Array
(
[id] => 7130135
[patent_doc_number] => 20040041164
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'Enhanced light extraction in leds through the use of internal and external optical elements'
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[patent_app_number] => 10/665595
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[firstpage_image] =>[orig_patent_app_number] => 10665595
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/665595 | Enhanced light extraction in LEDs through the use of internal and external optical elements | Sep 16, 2003 | Issued |
Array
(
[id] => 7301172
[patent_doc_number] => 20040113149
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[patent_kind] => A1
[patent_issue_date] => 2004-06-17
[patent_title] => 'Thin film transistor array panel and manufacturing method thereof'
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[patent_app_country] => US
[patent_app_date] => 2003-08-26
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10648544
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/648544 | Thin film transistor array panel and manufacturing method thereof | Aug 25, 2003 | Issued |
Array
(
[id] => 7614983
[patent_doc_number] => 06897543
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-24
[patent_title] => 'Electrically-programmable integrated circuit antifuses'
[patent_app_type] => utility
[patent_app_number] => 10/646013
[patent_app_country] => US
[patent_app_date] => 2003-08-22
[patent_effective_date] => 0000-00-00
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/897/06897543.pdf
[firstpage_image] =>[orig_patent_app_number] => 10646013
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/646013 | Electrically-programmable integrated circuit antifuses | Aug 21, 2003 | Issued |