Renee R. Berry

Array ( [id] => 7640343 [patent_doc_number] => 06395571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method for fabricating polysilicon TFT' [patent_app_type] => B1 [patent_app_number] => 09/665119 [patent_app_country] => US [patent_app_date] => 2000-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 3177 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395571.pdf [firstpage_image] =>[orig_patent_app_number] => 09665119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565919 [patent_doc_number] => 06376344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device' [patent_app_type] => B1 [patent_app_number] => 09/661659 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6084 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376344.pdf [firstpage_image] =>[orig_patent_app_number] => 09661659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1534489 [patent_doc_number] => 06489185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Protective film for the fabrication of direct build-up layers on an encapsulated die package' [patent_app_type] => B1 [patent_app_number] => 09/660755 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 4231 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489185.pdf [firstpage_image] =>[orig_patent_app_number] => 09660755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1519592 [patent_doc_number] => 06413317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Substrate processing method and substrate processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/661309 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8927 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413317.pdf [firstpage_image] =>[orig_patent_app_number] => 09661309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1514603 [patent_doc_number] => 06420282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD' [patent_app_type] => B1 [patent_app_number] => 09/658181 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4390 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420282.pdf [firstpage_image] =>[orig_patent_app_number] => 09658181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1412615 [patent_doc_number] => 06524946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method of fabricating a semiconductor device having a contact hole' [patent_app_type] => B1 [patent_app_number] => 09/657979 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 4352 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524946.pdf [firstpage_image] =>[orig_patent_app_number] => 09657979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1400352 [patent_doc_number] => 06545360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/657839 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 9667 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545360.pdf [firstpage_image] =>[orig_patent_app_number] => 09657839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478162 [patent_doc_number] => 06451684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Semiconductor device having a conductive layer side surface slope which is at least 90 and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/656889 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2707 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451684.pdf [firstpage_image] =>[orig_patent_app_number] => 09656889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585614 [patent_doc_number] => 06358840 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Forming and filling a recess in interconnect with alloy to minimize electromigration' [patent_app_type] => B1 [patent_app_number] => 09/655699 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3466 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358840.pdf [firstpage_image] =>[orig_patent_app_number] => 09655699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585514 [patent_doc_number] => 06358816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method for uniform polish in microelectronic device' [patent_app_type] => B1 [patent_app_number] => 09/655149 [patent_app_country] => US [patent_app_date] => 2000-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2747 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358816.pdf [firstpage_image] =>[orig_patent_app_number] => 09655149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 638319 [patent_doc_number] => 07126195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Method for forming a metallization layer' [patent_app_type] => utility [patent_app_number] => 09/652619 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1889 [patent_no_of_claims] => 107 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126195.pdf [firstpage_image] =>[orig_patent_app_number] => 09652619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1453632 [patent_doc_number] => 06461962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Etching method' [patent_app_type] => B1 [patent_app_number] => 09/650647 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3175 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461962.pdf [firstpage_image] =>[orig_patent_app_number] => 09650647 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1467008 [patent_doc_number] => 06458669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method of manufacturing an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/650606 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3146 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458669.pdf [firstpage_image] =>[orig_patent_app_number] => 09650606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1299717 [patent_doc_number] => 06624051 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Semiconductor thin film and semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/645329 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 61 [patent_no_of_words] => 12971 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624051.pdf [firstpage_image] =>[orig_patent_app_number] => 09645329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1370919 [patent_doc_number] => 06562640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method of manufacturing micro-display' [patent_app_type] => B1 [patent_app_number] => 09/644235 [patent_app_country] => US [patent_app_date] => 2000-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2169 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562640.pdf [firstpage_image] =>[orig_patent_app_number] => 09644235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1602570 [patent_doc_number] => 06432749 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of fabricating flip chip IC packages with heat spreaders in strip format' [patent_app_type] => B1 [patent_app_number] => 09/643646 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4632 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432749.pdf [firstpage_image] =>[orig_patent_app_number] => 09643646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1558021 [patent_doc_number] => 06436195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method of fabricating a MOS device' [patent_app_type] => B1 [patent_app_number] => 09/643777 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1719 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436195.pdf [firstpage_image] =>[orig_patent_app_number] => 09643777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1381565 [patent_doc_number] => 06551872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method for making integrated circuit including interconnects with enhanced electromigration resistance using doped seed layer and integrated circuits produced thereby' [patent_app_type] => B1 [patent_app_number] => 09/642140 [patent_app_country] => US [patent_app_date] => 2000-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3096 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551872.pdf [firstpage_image] =>[orig_patent_app_number] => 09642140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549585 [patent_doc_number] => 06346430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Packaged integrated processor and spatial light modulator' [patent_app_type] => B1 [patent_app_number] => 09/641189 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2560 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346430.pdf [firstpage_image] =>[orig_patent_app_number] => 09641189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1354354 [patent_doc_number] => 06576509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/639305 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 46 [patent_no_of_words] => 11649 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576509.pdf [firstpage_image] =>[orig_patent_app_number] => 09639305 [rel_patent_id] =>[rel_patent_doc_number] =>)