Search

Renee R. Berry

Examiner (ID: 18563)

Most Active Art Unit
2818
Art Unit(s)
2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818
Total Applications
592
Issued Applications
546
Pending Applications
22
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1212806 [patent_doc_number] => 06709968 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Microelectronic device with package with conductive elements and associated method of manufacture' [patent_app_type] => B1 [patent_app_number] => 09/640149 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5609 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709968.pdf [firstpage_image] =>[orig_patent_app_number] => 09640149 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640149
Microelectronic device with package with conductive elements and associated method of manufacture Aug 15, 2000 Issued
Array ( [id] => 1302801 [patent_doc_number] => 06620674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Semiconductor device with self-aligned contact and its manufacture' [patent_app_type] => B1 [patent_app_number] => 09/638139 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 76 [patent_no_of_words] => 16501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620674.pdf [firstpage_image] =>[orig_patent_app_number] => 09638139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638139
Semiconductor device with self-aligned contact and its manufacture Aug 14, 2000 Issued
Array ( [id] => 1367317 [patent_doc_number] => 06566223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'High voltage integrated switching devices on a bonded and trenched silicon substrate' [patent_app_type] => B1 [patent_app_number] => 09/638710 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5019 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566223.pdf [firstpage_image] =>[orig_patent_app_number] => 09638710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638710
High voltage integrated switching devices on a bonded and trenched silicon substrate Aug 14, 2000 Issued
Array ( [id] => 1500434 [patent_doc_number] => 06486062 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Selective deposition of amorphous silicon for formation of nickel silicide with smooth interface on N-doped substrate' [patent_app_type] => B1 [patent_app_number] => 09/636510 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3195 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486062.pdf [firstpage_image] =>[orig_patent_app_number] => 09636510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/636510
Selective deposition of amorphous silicon for formation of nickel silicide with smooth interface on N-doped substrate Aug 9, 2000 Issued
Array ( [id] => 1600187 [patent_doc_number] => 06475826 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Method and system for detection of integrated circuit package orientation in a tape and reel system' [patent_app_type] => B1 [patent_app_number] => 09/632498 [patent_app_country] => US [patent_app_date] => 2000-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1458 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475826.pdf [firstpage_image] =>[orig_patent_app_number] => 09632498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632498
Method and system for detection of integrated circuit package orientation in a tape and reel system Aug 2, 2000 Issued
Array ( [id] => 1581189 [patent_doc_number] => 06423624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Ball array layout' [patent_app_type] => B1 [patent_app_number] => 09/631259 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7173 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423624.pdf [firstpage_image] =>[orig_patent_app_number] => 09631259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/631259
Ball array layout Aug 1, 2000 Issued
Array ( [id] => 1542365 [patent_doc_number] => 06372522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Use of optimized film stacks for increasing absorption for laser repair of fuse links' [patent_app_type] => B1 [patent_app_number] => 09/631059 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3273 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372522.pdf [firstpage_image] =>[orig_patent_app_number] => 09631059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/631059
Use of optimized film stacks for increasing absorption for laser repair of fuse links Jul 31, 2000 Issued
Array ( [id] => 1424461 [patent_doc_number] => 06503823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method for manufacturing capacitor elements on a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/626005 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2112 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503823.pdf [firstpage_image] =>[orig_patent_app_number] => 09626005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/626005
Method for manufacturing capacitor elements on a semiconductor substrate Jul 25, 2000 Issued
Array ( [id] => 1574802 [patent_doc_number] => 06468906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Passivation of copper interconnect surfaces with a passivating metal layer' [patent_app_type] => B1 [patent_app_number] => 09/617009 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 4460 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468906.pdf [firstpage_image] =>[orig_patent_app_number] => 09617009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/617009
Passivation of copper interconnect surfaces with a passivating metal layer Jul 13, 2000 Issued
Array ( [id] => 1600571 [patent_doc_number] => 06475923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Group III nitride compound semiconductor thin film and deposition method thereof, and semiconductor device and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/616688 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 9458 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475923.pdf [firstpage_image] =>[orig_patent_app_number] => 09616688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/616688
Group III nitride compound semiconductor thin film and deposition method thereof, and semiconductor device and manufacturing method thereof Jul 13, 2000 Issued
Array ( [id] => 1411822 [patent_doc_number] => 06524896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 09/617105 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 51 [patent_no_of_words] => 10923 [patent_no_of_claims] => 78 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524896.pdf [firstpage_image] =>[orig_patent_app_number] => 09617105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/617105
Semiconductor device and method of fabricating the same Jul 13, 2000 Issued
Array ( [id] => 1517313 [patent_doc_number] => 06500742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Construction of a film on a semiconductor wafer' [patent_app_type] => B1 [patent_app_number] => 09/617515 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 62 [patent_no_of_words] => 21173 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500742.pdf [firstpage_image] =>[orig_patent_app_number] => 09617515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/617515
Construction of a film on a semiconductor wafer Jul 13, 2000 Issued
Array ( [id] => 4267224 [patent_doc_number] => 06306741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method of patterning gate electrodes with high K gate dielectrics' [patent_app_type] => 1 [patent_app_number] => 9/615809 [patent_app_country] => US [patent_app_date] => 2000-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1550 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306741.pdf [firstpage_image] =>[orig_patent_app_number] => 615809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/615809
Method of patterning gate electrodes with high K gate dielectrics Jul 12, 2000 Issued
Array ( [id] => 1517239 [patent_doc_number] => 06500714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and structure for manufacturing ROMs in a semiconductor process' [patent_app_type] => B1 [patent_app_number] => 09/607769 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1654 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500714.pdf [firstpage_image] =>[orig_patent_app_number] => 09607769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607769
Method and structure for manufacturing ROMs in a semiconductor process Jun 29, 2000 Issued
Array ( [id] => 1532498 [patent_doc_number] => 06410398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Device for the adjustment of circuits after packaging, corresponding fabrication process and induction device' [patent_app_type] => B1 [patent_app_number] => 09/604989 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4715 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410398.pdf [firstpage_image] =>[orig_patent_app_number] => 09604989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604989
Device for the adjustment of circuits after packaging, corresponding fabrication process and induction device Jun 27, 2000 Issued
Array ( [id] => 1490328 [patent_doc_number] => 06417102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Semiconductor processing method using high pressure liquid media treatment' [patent_app_type] => B1 [patent_app_number] => 09/603849 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2195 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417102.pdf [firstpage_image] =>[orig_patent_app_number] => 09603849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603849
Semiconductor processing method using high pressure liquid media treatment Jun 25, 2000 Issued
Array ( [id] => 4395079 [patent_doc_number] => 06297127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Self-aligned deep trench isolation to shallow trench isolation' [patent_app_type] => 1 [patent_app_number] => 9/599699 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 1335 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297127.pdf [firstpage_image] =>[orig_patent_app_number] => 599699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599699
Self-aligned deep trench isolation to shallow trench isolation Jun 21, 2000 Issued
Array ( [id] => 1574799 [patent_doc_number] => 06468905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Methods of restricting silicon migration' [patent_app_type] => B1 [patent_app_number] => 09/596231 [patent_app_country] => US [patent_app_date] => 2000-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2285 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468905.pdf [firstpage_image] =>[orig_patent_app_number] => 09596231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596231
Methods of restricting silicon migration Jun 12, 2000 Issued
Array ( [id] => 1561230 [patent_doc_number] => 06362100 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Methods and apparatus for forming a copper interconnect' [patent_app_type] => B1 [patent_app_number] => 09/589839 [patent_app_country] => US [patent_app_date] => 2000-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3279 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362100.pdf [firstpage_image] =>[orig_patent_app_number] => 09589839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/589839
Methods and apparatus for forming a copper interconnect Jun 7, 2000 Issued
Array ( [id] => 1550587 [patent_doc_number] => 06399518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Resist coating and developing processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/576889 [patent_app_country] => US [patent_app_date] => 2000-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7271 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399518.pdf [firstpage_image] =>[orig_patent_app_number] => 09576889 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/576889
Resist coating and developing processing apparatus May 23, 2000 Issued
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