Renee R. Berry

Array ( [id] => 1559889 [patent_doc_number] => 06436824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Low dielectric constant materials for copper damascene' [patent_app_type] => B1 [patent_app_number] => 09/346526 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2370 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436824.pdf [firstpage_image] =>[orig_patent_app_number] => 09346526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549697 [patent_doc_number] => 06346451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode' [patent_app_type] => B1 [patent_app_number] => 09/343912 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2905 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346451.pdf [firstpage_image] =>[orig_patent_app_number] => 09343912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553645 [patent_doc_number] => 06348421 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD' [patent_app_type] => B1 [patent_app_number] => 09/334288 [patent_app_country] => US [patent_app_date] => 1999-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1736 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348421.pdf [firstpage_image] =>[orig_patent_app_number] => 09334288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4406260 [patent_doc_number] => 06171949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Low energy passivation of conductive material in damascene process for semiconductors' [patent_app_type] => 1 [patent_app_number] => 9/329155 [patent_app_country] => US [patent_app_date] => 1999-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2528 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171949.pdf [firstpage_image] =>[orig_patent_app_number] => 329155 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4271811 [patent_doc_number] => 06323138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Capacitor, methods of forming capacitors, methods for forming silicon nitride layers on silicon-comprising substrates, and methods of densifying silicon nitride layers' [patent_app_type] => 1 [patent_app_number] => 9/328313 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3159 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323138.pdf [firstpage_image] =>[orig_patent_app_number] => 328313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4357629 [patent_doc_number] => 06174812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Copper damascene technology for ultra large scale integration circuits' [patent_app_type] => 1 [patent_app_number] => 9/328246 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 1781 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174812.pdf [firstpage_image] =>[orig_patent_app_number] => 328246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366545 [patent_doc_number] => 06274471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique' [patent_app_type] => 1 [patent_app_number] => 9/325953 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274471.pdf [firstpage_image] =>[orig_patent_app_number] => 325953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1346678 [patent_doc_number] => 06583058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Solid hermetic via and bump fabrication' [patent_app_type] => B1 [patent_app_number] => 09/326215 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 16 [patent_no_of_words] => 2884 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583058.pdf [firstpage_image] =>[orig_patent_app_number] => 09326215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408771 [patent_doc_number] => 06309983 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Low temperature sacrificial oxide formation' [patent_app_type] => 1 [patent_app_number] => 9/324926 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3486 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309983.pdf [firstpage_image] =>[orig_patent_app_number] => 324926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1532568 [patent_doc_number] => 06410416 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Article comprising a high-resolution pattern on a non-planar surface and method of making the same' [patent_app_type] => B1 [patent_app_number] => 09/322471 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 4127 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410416.pdf [firstpage_image] =>[orig_patent_app_number] => 09322471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4360463 [patent_doc_number] => 06302312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Bonding apparatus and method' [patent_app_type] => 1 [patent_app_number] => 9/322801 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2489 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/302/06302312.pdf [firstpage_image] =>[orig_patent_app_number] => 322801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1565643 [patent_doc_number] => 06376285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Annealed porous silicon with epitaxial layer for SOI' [patent_app_type] => B1 [patent_app_number] => 09/314983 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2205 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376285.pdf [firstpage_image] =>[orig_patent_app_number] => 09314983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4404200 [patent_doc_number] => 06271047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Layer-thickness detection methods and apparatus for wafers and the like, and polishing apparatus comprising same' [patent_app_type] => 1 [patent_app_number] => 9/316082 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 17118 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271047.pdf [firstpage_image] =>[orig_patent_app_number] => 316082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259488 [patent_doc_number] => 06258711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Sacrificial deposit to improve damascene pattern planarization in semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 9/294406 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3523 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258711.pdf [firstpage_image] =>[orig_patent_app_number] => 294406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354809 [patent_doc_number] => 06218317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Methylated oxide-type dielectric as a replacement for SiO2 hardmasks used in polymeric low K, dual damascene interconnect integration' [patent_app_type] => 1 [patent_app_number] => 9/294914 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1202 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218317.pdf [firstpage_image] =>[orig_patent_app_number] => 294914 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549772 [patent_doc_number] => 06346470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method for reducing electromigration in semiconductor interconnect lines' [patent_app_type] => B1 [patent_app_number] => 09/294454 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1778 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346470.pdf [firstpage_image] =>[orig_patent_app_number] => 09294454 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1446638 [patent_doc_number] => 06368957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/292666 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5635 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368957.pdf [firstpage_image] =>[orig_patent_app_number] => 09292666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4271681 [patent_doc_number] => 06323129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Process for maintaining a semiconductor substrate layer deposition equipment chamber in a preconditioned and low particulate state' [patent_app_type] => 1 [patent_app_number] => 9/285635 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3718 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323129.pdf [firstpage_image] =>[orig_patent_app_number] => 285635 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1585645 [patent_doc_number] => 06358847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method for enabling conventional wire bonding to copper-based bond pad features' [patent_app_type] => B1 [patent_app_number] => 09/282596 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6080 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358847.pdf [firstpage_image] =>[orig_patent_app_number] => 09282596 [rel_patent_id] =>[rel_patent_doc_number] =>)