Search

Renee R. Berry

Examiner (ID: 18563)

Most Active Art Unit
2818
Art Unit(s)
2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818
Total Applications
592
Issued Applications
546
Pending Applications
22
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4390643 [patent_doc_number] => 06278331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'System and method for compensating wafer parameters' [patent_app_type] => 1 [patent_app_number] => 9/282081 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2076 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278331.pdf [firstpage_image] =>[orig_patent_app_number] => 282081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282081
System and method for compensating wafer parameters Mar 29, 1999 Issued
Array ( [id] => 4250480 [patent_doc_number] => 06207555 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Electron beam process during dual damascene processing' [patent_app_type] => 1 [patent_app_number] => 9/270536 [patent_app_country] => US [patent_app_date] => 1999-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 32 [patent_no_of_words] => 10082 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207555.pdf [firstpage_image] =>[orig_patent_app_number] => 270536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270536
Electron beam process during dual damascene processing Mar 16, 1999 Issued
Array ( [id] => 4302577 [patent_doc_number] => 06251777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Thermal annealing method for forming metal silicide layer' [patent_app_type] => 1 [patent_app_number] => 9/261994 [patent_app_country] => US [patent_app_date] => 1999-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251777.pdf [firstpage_image] =>[orig_patent_app_number] => 261994 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261994
Thermal annealing method for forming metal silicide layer Mar 4, 1999 Issued
Array ( [id] => 1412700 [patent_doc_number] => 06524951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon' [patent_app_type] => B2 [patent_app_number] => 09/259216 [patent_app_country] => US [patent_app_date] => 1999-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3304 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524951.pdf [firstpage_image] =>[orig_patent_app_number] => 09259216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/259216
Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon Feb 28, 1999 Issued
Array ( [id] => 1564812 [patent_doc_number] => 06338975 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Optical circuit device, its manufacturing process and a multilayer optical circuit using said optical circuit device' [patent_app_type] => B1 [patent_app_number] => 09/257248 [patent_app_country] => US [patent_app_date] => 1999-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 125 [patent_no_of_words] => 15220 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 29 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/338/06338975.pdf [firstpage_image] =>[orig_patent_app_number] => 09257248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/257248
Optical circuit device, its manufacturing process and a multilayer optical circuit using said optical circuit device Feb 24, 1999 Issued
Array ( [id] => 4353065 [patent_doc_number] => 06218199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Silicon substrate with identification data' [patent_app_type] => 1 [patent_app_number] => 9/253522 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3344 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218199.pdf [firstpage_image] =>[orig_patent_app_number] => 253522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/253522
Silicon substrate with identification data Feb 18, 1999 Issued
Array ( [id] => 6141810 [patent_doc_number] => 20020001928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'METHOD FOR PERFORMING METALLO-ORGANIC CHEMICAL VAPOR DEPOSITION OF TITANIUM NITRIDE AT REDUCED TEMPERATURE' [patent_app_type] => new [patent_app_number] => 09/248183 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7165 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001928.pdf [firstpage_image] =>[orig_patent_app_number] => 09248183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/248183
Method for performing metallo-organic chemical vapor deposition of titanium nitride at reduced temperature Feb 8, 1999 Issued
Array ( [id] => 1490206 [patent_doc_number] => 06417068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Semiconductor device navigation using laser scribing' [patent_app_type] => B1 [patent_app_number] => 09/247001 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4143 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417068.pdf [firstpage_image] =>[orig_patent_app_number] => 09247001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/247001
Semiconductor device navigation using laser scribing Feb 7, 1999 Issued
Array ( [id] => 7644008 [patent_doc_number] => 06429030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method for testing a semiconductor die using wells' [patent_app_type] => B1 [patent_app_number] => 09/246633 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3843 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429030.pdf [firstpage_image] =>[orig_patent_app_number] => 09246633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246633
Method for testing a semiconductor die using wells Feb 7, 1999 Issued
Array ( [id] => 4084467 [patent_doc_number] => 06162726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Gas shielding during plating' [patent_app_type] => 1 [patent_app_number] => 9/245088 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5565 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162726.pdf [firstpage_image] =>[orig_patent_app_number] => 245088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245088
Gas shielding during plating Feb 4, 1999 Issued
Array ( [id] => 4259818 [patent_doc_number] => 06258732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method of forming a patterned organic dielectric layer on a substrate' [patent_app_type] => 1 [patent_app_number] => 9/244936 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3667 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258732.pdf [firstpage_image] =>[orig_patent_app_number] => 244936 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244936
Method of forming a patterned organic dielectric layer on a substrate Feb 3, 1999 Issued
Array ( [id] => 1520770 [patent_doc_number] => 06413883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method of liquid deposition by selection of liquid viscosity and other precursor properties' [patent_app_type] => B1 [patent_app_number] => 09/243254 [patent_app_country] => US [patent_app_date] => 1999-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 8410 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413883.pdf [firstpage_image] =>[orig_patent_app_number] => 09243254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/243254
Method of liquid deposition by selection of liquid viscosity and other precursor properties Feb 2, 1999 Issued
Array ( [id] => 4365451 [patent_doc_number] => 06274394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method and system for determining the fail patterns of fabricated wafers in automated wafer acceptance test' [patent_app_type] => 1 [patent_app_number] => 9/237181 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3362 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274394.pdf [firstpage_image] =>[orig_patent_app_number] => 237181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237181
Method and system for determining the fail patterns of fabricated wafers in automated wafer acceptance test Jan 24, 1999 Issued
Array ( [id] => 4394207 [patent_doc_number] => 06297065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method to rework device with faulty metal stack layer' [patent_app_type] => 1 [patent_app_number] => 9/229006 [patent_app_country] => US [patent_app_date] => 1999-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3088 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297065.pdf [firstpage_image] =>[orig_patent_app_number] => 229006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/229006
Method to rework device with faulty metal stack layer Jan 11, 1999 Issued
Array ( [id] => 4259545 [patent_doc_number] => 06258715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Process for low-k dielectric with dummy plugs' [patent_app_type] => 1 [patent_app_number] => 9/228125 [patent_app_country] => US [patent_app_date] => 1999-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2472 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258715.pdf [firstpage_image] =>[orig_patent_app_number] => 228125 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/228125
Process for low-k dielectric with dummy plugs Jan 10, 1999 Issued
Array ( [id] => 4366868 [patent_doc_number] => 06274493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for forming a via' [patent_app_type] => 1 [patent_app_number] => 9/227975 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2149 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274493.pdf [firstpage_image] =>[orig_patent_app_number] => 227975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227975
Method for forming a via Jan 7, 1999 Issued
Array ( [id] => 4267238 [patent_doc_number] => 06306742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method for forming a high dielectric constant insulator in the fabrication of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/225659 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2672 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306742.pdf [firstpage_image] =>[orig_patent_app_number] => 225659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225659
Method for forming a high dielectric constant insulator in the fabrication of an integrated circuit Jan 4, 1999 Issued
Array ( [id] => 4188878 [patent_doc_number] => 06153514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer' [patent_app_type] => 1 [patent_app_number] => 9/225215 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4157 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153514.pdf [firstpage_image] =>[orig_patent_app_number] => 225215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225215
Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer Jan 3, 1999 Issued
Array ( [id] => 4287174 [patent_doc_number] => 06268285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of removing plasma etch damage to pre-silicidized surfaces by wet silicon etch' [patent_app_type] => 1 [patent_app_number] => 9/225214 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2547 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268285.pdf [firstpage_image] =>[orig_patent_app_number] => 225214 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225214
Method of removing plasma etch damage to pre-silicidized surfaces by wet silicon etch Jan 3, 1999 Issued
Array ( [id] => 4354855 [patent_doc_number] => 06218320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method for improving the uniformity of wafer-to-wafer film thickness' [patent_app_type] => 1 [patent_app_number] => 9/222654 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2094 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218320.pdf [firstpage_image] =>[orig_patent_app_number] => 222654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222654
Method for improving the uniformity of wafer-to-wafer film thickness Dec 29, 1998 Issued
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