Search

Renee R. Berry

Examiner (ID: 18563)

Most Active Art Unit
2818
Art Unit(s)
2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818
Total Applications
592
Issued Applications
546
Pending Applications
22
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6141845 [patent_doc_number] => 20020001947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'SEMICONDUCTOR PROCESSING METHOD USING HIGH PRESSURE LIQUID MEDIA TREATMENT' [patent_app_type] => new [patent_app_number] => 09/146116 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2193 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001947.pdf [firstpage_image] =>[orig_patent_app_number] => 09146116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146116
Semiconductor processing method using high pressure liquid media treatment Sep 1, 1998 Issued
Array ( [id] => 4242286 [patent_doc_number] => 06144050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Electronic devices with strontium barrier film and process for making same' [patent_app_type] => 1 [patent_app_number] => 9/137085 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8245 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144050.pdf [firstpage_image] =>[orig_patent_app_number] => 137085 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137085
Electronic devices with strontium barrier film and process for making same Aug 19, 1998 Issued
Array ( [id] => 4102265 [patent_doc_number] => 06100185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line' [patent_app_type] => 1 [patent_app_number] => 9/134624 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2780 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100185.pdf [firstpage_image] =>[orig_patent_app_number] => 134624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134624
Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line Aug 13, 1998 Issued
Array ( [id] => 4153471 [patent_doc_number] => 06107170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Silicon sensor contact with platinum silicide, titanium/tungsten and gold' [patent_app_type] => 1 [patent_app_number] => 9/129195 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1569 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107170.pdf [firstpage_image] =>[orig_patent_app_number] => 129195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129195
Silicon sensor contact with platinum silicide, titanium/tungsten and gold Jul 23, 1998 Issued
Array ( [id] => 4102094 [patent_doc_number] => 06100173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process' [patent_app_type] => 1 [patent_app_number] => 9/116066 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4272 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100173.pdf [firstpage_image] =>[orig_patent_app_number] => 116066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/116066
Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process Jul 14, 1998 Issued
Array ( [id] => 4235939 [patent_doc_number] => 06165896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Self-aligned formation and method for semiconductors' [patent_app_type] => 1 [patent_app_number] => 9/105226 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4292 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165896.pdf [firstpage_image] =>[orig_patent_app_number] => 105226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105226
Self-aligned formation and method for semiconductors Jun 24, 1998 Issued
Array ( [id] => 4290219 [patent_doc_number] => 06235627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/103374 [patent_app_country] => US [patent_app_date] => 1998-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 52 [patent_no_of_words] => 8428 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235627.pdf [firstpage_image] =>[orig_patent_app_number] => 103374 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/103374
Semiconductor device and method for manufacturing the same Jun 23, 1998 Issued
Array ( [id] => 4215087 [patent_doc_number] => 06110826 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Dual damascene process using selective W CVD' [patent_app_type] => 1 [patent_app_number] => 9/092816 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 19 [patent_no_of_words] => 4872 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110826.pdf [firstpage_image] =>[orig_patent_app_number] => 092816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092816
Dual damascene process using selective W CVD Jun 7, 1998 Issued
Array ( [id] => 4292771 [patent_doc_number] => 06180515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method of fabricating self-align contact window with silicon nitride side wall' [patent_app_type] => 1 [patent_app_number] => 9/090726 [patent_app_country] => US [patent_app_date] => 1998-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 3182 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180515.pdf [firstpage_image] =>[orig_patent_app_number] => 090726 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090726
Method of fabricating self-align contact window with silicon nitride side wall Jun 3, 1998 Issued
Array ( [id] => 1566085 [patent_doc_number] => 06376374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece' [patent_app_type] => B1 [patent_app_number] => 09/076565 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5439 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376374.pdf [firstpage_image] =>[orig_patent_app_number] => 09076565 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076565
Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece May 11, 1998 Issued
Array ( [id] => 4139658 [patent_doc_number] => 06060389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect' [patent_app_type] => 1 [patent_app_number] => 9/075596 [patent_app_country] => US [patent_app_date] => 1998-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060389.pdf [firstpage_image] =>[orig_patent_app_number] => 075596 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/075596
Semiconductor fabrication employing a conformal layer of CVD deposited TiN at the periphery of an interconnect May 10, 1998 Issued
Array ( [id] => 4131831 [patent_doc_number] => 06121138 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging' [patent_app_type] => 1 [patent_app_number] => 9/069014 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4840 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121138.pdf [firstpage_image] =>[orig_patent_app_number] => 069014 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069014
Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging Apr 27, 1998 Issued
Array ( [id] => 4215684 [patent_doc_number] => 06087250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/064875 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 4938 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087250.pdf [firstpage_image] =>[orig_patent_app_number] => 064875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064875
Semiconductor device having multilayered metal interconnection structure and manufacturing method thereof Apr 22, 1998 Issued
Array ( [id] => 4131818 [patent_doc_number] => 06121137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/028374 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 9967 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121137.pdf [firstpage_image] =>[orig_patent_app_number] => 028374 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/028374
Method of fabricating semiconductor device Feb 23, 1998 Issued
Array ( [id] => 4107847 [patent_doc_number] => 06057223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Passivated copper conductive layers for microelectronic applications' [patent_app_type] => 1 [patent_app_number] => 9/021666 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057223.pdf [firstpage_image] =>[orig_patent_app_number] => 021666 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021666
Passivated copper conductive layers for microelectronic applications Feb 9, 1998 Issued
Array ( [id] => 4070476 [patent_doc_number] => 06069031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Process to form CMOS devices with higher ESD and hot carrier immunity' [patent_app_type] => 1 [patent_app_number] => 9/013694 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3359 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069031.pdf [firstpage_image] =>[orig_patent_app_number] => 013694 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013694
Process to form CMOS devices with higher ESD and hot carrier immunity Jan 25, 1998 Issued
Array ( [id] => 4169791 [patent_doc_number] => 06140234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method to selectively fill recesses with conductive metal' [patent_app_type] => 1 [patent_app_number] => 9/009824 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3578 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140234.pdf [firstpage_image] =>[orig_patent_app_number] => 009824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/009824
Method to selectively fill recesses with conductive metal Jan 19, 1998 Issued
Array ( [id] => 4406358 [patent_doc_number] => 06171958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Process for preparation of diffusion barrier for semiconductor' [patent_app_type] => 1 [patent_app_number] => 9/006948 [patent_app_country] => US [patent_app_date] => 1998-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1951 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171958.pdf [firstpage_image] =>[orig_patent_app_number] => 006948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006948
Process for preparation of diffusion barrier for semiconductor Jan 13, 1998 Issued
Array ( [id] => 4419673 [patent_doc_number] => 06177337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method of reducing metal voids in semiconductor device interconnection' [patent_app_type] => 1 [patent_app_number] => 9/003102 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3766 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177337.pdf [firstpage_image] =>[orig_patent_app_number] => 003102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003102
Method of reducing metal voids in semiconductor device interconnection Jan 5, 1998 Issued
Array ( [id] => 4234237 [patent_doc_number] => 06074944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Methods for priming wafers employed in integrated circuit devices using dihydropyrane' [patent_app_type] => 1 [patent_app_number] => 9/002636 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1730 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074944.pdf [firstpage_image] =>[orig_patent_app_number] => 002636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002636
Methods for priming wafers employed in integrated circuit devices using dihydropyrane Jan 4, 1998 Issued
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