Search

Renee R. Berry

Examiner (ID: 18563)

Most Active Art Unit
2818
Art Unit(s)
2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818
Total Applications
592
Issued Applications
546
Pending Applications
22
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4358301 [patent_doc_number] => 06191048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Process for manufacturing composite glass/Si substrates for microwave integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 9/001828 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4666 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191048.pdf [firstpage_image] =>[orig_patent_app_number] => 001828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001828
Process for manufacturing composite glass/Si substrates for microwave integrated circuit fabrication Dec 30, 1997 Issued
Array ( [id] => 4153797 [patent_doc_number] => 06107192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Reactive preclean prior to metallization for sub-quarter micron application' [patent_app_type] => 1 [patent_app_number] => 9/000746 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107192.pdf [firstpage_image] =>[orig_patent_app_number] => 000746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000746
Reactive preclean prior to metallization for sub-quarter micron application Dec 29, 1997 Issued
Array ( [id] => 4125756 [patent_doc_number] => 06127284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method of manufacturing a semiconductor device having nitrogen-bearing oxide gate insulating layer' [patent_app_type] => 1 [patent_app_number] => 8/993416 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2407 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127284.pdf [firstpage_image] =>[orig_patent_app_number] => 993416 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993416
Method of manufacturing a semiconductor device having nitrogen-bearing oxide gate insulating layer Dec 17, 1997 Issued
Array ( [id] => 4183857 [patent_doc_number] => 06159856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method of manufacturing a semiconductor device with a silicide layer' [patent_app_type] => 1 [patent_app_number] => 8/993865 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 8916 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159856.pdf [firstpage_image] =>[orig_patent_app_number] => 993865 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993865
Method of manufacturing a semiconductor device with a silicide layer Dec 17, 1997 Issued
Array ( [id] => 4148238 [patent_doc_number] => 06156121 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Wafer boat and film formation method' [patent_app_type] => 1 [patent_app_number] => 8/991208 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 8371 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156121.pdf [firstpage_image] =>[orig_patent_app_number] => 991208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991208
Wafer boat and film formation method Dec 15, 1997 Issued
Array ( [id] => 4348549 [patent_doc_number] => 06214724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor device and manufacturing method therefor' [patent_app_type] => 1 [patent_app_number] => 8/988554 [patent_app_country] => US [patent_app_date] => 1997-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6709 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214724.pdf [firstpage_image] =>[orig_patent_app_number] => 988554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/988554
Semiconductor device and manufacturing method therefor Dec 10, 1997 Issued
Array ( [id] => 4407853 [patent_doc_number] => 06239042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices' [patent_app_type] => 1 [patent_app_number] => 8/987454 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3880 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239042.pdf [firstpage_image] =>[orig_patent_app_number] => 987454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987454
Process for realizing an intermediate dielectric layer for enhancing the planarity in semiconductor electronic devices Dec 8, 1997 Issued
Array ( [id] => 4169805 [patent_doc_number] => 06140235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'High pressure copper fill at low temperature' [patent_app_type] => 1 [patent_app_number] => 8/985844 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4515 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140235.pdf [firstpage_image] =>[orig_patent_app_number] => 985844 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985844
High pressure copper fill at low temperature Dec 4, 1997 Issued
Array ( [id] => 4155678 [patent_doc_number] => 06114242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'MOCVD molybdenum nitride diffusion barrier for Cu metallization' [patent_app_type] => 1 [patent_app_number] => 8/985404 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 1865 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114242.pdf [firstpage_image] =>[orig_patent_app_number] => 985404 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985404
MOCVD molybdenum nitride diffusion barrier for Cu metallization Dec 4, 1997 Issued
Array ( [id] => 4155146 [patent_doc_number] => 06103639 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of reducing pin holes in a nitride passivation layer' [patent_app_type] => 1 [patent_app_number] => 8/984354 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1315 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103639.pdf [firstpage_image] =>[orig_patent_app_number] => 984354 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984354
Method of reducing pin holes in a nitride passivation layer Dec 2, 1997 Issued
Array ( [id] => 4405268 [patent_doc_number] => 06271129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method for forming a gap filling refractory metal layer having reduced stress' [patent_app_type] => 1 [patent_app_number] => 8/984438 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5580 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271129.pdf [firstpage_image] =>[orig_patent_app_number] => 984438 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984438
Method for forming a gap filling refractory metal layer having reduced stress Dec 2, 1997 Issued
Array ( [id] => 4205288 [patent_doc_number] => 06077780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure' [patent_app_type] => 1 [patent_app_number] => 8/984352 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 2640 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077780.pdf [firstpage_image] =>[orig_patent_app_number] => 984352 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984352
Method for filling high aspect ratio openings of an integrated circuit to minimize electromigration failure Dec 2, 1997 Issued
Array ( [id] => 4125471 [patent_doc_number] => 06127266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Stabilization of the interface between tiN and A1 alloys' [patent_app_type] => 1 [patent_app_number] => 8/979956 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3450 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127266.pdf [firstpage_image] =>[orig_patent_app_number] => 979956 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979956
Stabilization of the interface between tiN and A1 alloys Nov 25, 1997 Issued
Array ( [id] => 3938033 [patent_doc_number] => 05981389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method for producing a device having a chromium layer' [patent_app_type] => 1 [patent_app_number] => 8/977949 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2695 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981389.pdf [firstpage_image] =>[orig_patent_app_number] => 977949 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977949
Method for producing a device having a chromium layer Nov 24, 1997 Issued
Array ( [id] => 4259030 [patent_doc_number] => 06204174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for high rate deposition of tungsten' [patent_app_type] => 1 [patent_app_number] => 8/977831 [patent_app_country] => US [patent_app_date] => 1997-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7271 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204174.pdf [firstpage_image] =>[orig_patent_app_number] => 977831 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977831
Method for high rate deposition of tungsten Nov 24, 1997 Issued
Array ( [id] => 4357841 [patent_doc_number] => 06174823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Methods of forming a barrier layer' [patent_app_type] => 1 [patent_app_number] => 8/975705 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4047 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174823.pdf [firstpage_image] =>[orig_patent_app_number] => 975705 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975705
Methods of forming a barrier layer Nov 20, 1997 Issued
Array ( [id] => 4131671 [patent_doc_number] => 06146989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method of fabricating semiconductor device with cavity interposed between wirings' [patent_app_type] => 1 [patent_app_number] => 8/975046 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3530 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146989.pdf [firstpage_image] =>[orig_patent_app_number] => 975046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975046
Method of fabricating semiconductor device with cavity interposed between wirings Nov 19, 1997 Issued
Array ( [id] => 4344761 [patent_doc_number] => 06284650 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Integrated tungsten-silicide processes' [patent_app_type] => 1 [patent_app_number] => 8/969627 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4477 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284650.pdf [firstpage_image] =>[orig_patent_app_number] => 969627 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/969627
Integrated tungsten-silicide processes Nov 12, 1997 Issued
Array ( [id] => 4236183 [patent_doc_number] => 06165914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method for fabricating semiconductor devices with thick high quality oxides' [patent_app_type] => 1 [patent_app_number] => 8/968149 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1380 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165914.pdf [firstpage_image] =>[orig_patent_app_number] => 968149 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968149
Method for fabricating semiconductor devices with thick high quality oxides Nov 11, 1997 Issued
Array ( [id] => 4146301 [patent_doc_number] => 06063713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Methods for forming silicon nitride layers on silicon-comprising substrates' [patent_app_type] => 1 [patent_app_number] => 8/967766 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3158 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063713.pdf [firstpage_image] =>[orig_patent_app_number] => 967766 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967766
Methods for forming silicon nitride layers on silicon-comprising substrates Nov 9, 1997 Issued
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