
Renee R. Berry
Examiner (ID: 18563)
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818 |
| Total Applications | 592 |
| Issued Applications | 546 |
| Pending Applications | 22 |
| Abandoned Applications | 24 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4132151
[patent_doc_number] => 06121158
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Method for hardening a photoresist material formed on a substrate'
[patent_app_type] => 1
[patent_app_number] => 8/910308
[patent_app_country] => US
[patent_app_date] => 1997-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3852
[patent_no_of_claims] => 28
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/121/06121158.pdf
[firstpage_image] =>[orig_patent_app_number] => 910308
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/910308 | Method for hardening a photoresist material formed on a substrate | Aug 12, 1997 | Issued |
Array
(
[id] => 4155706
[patent_doc_number] => 06114244
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Method for manufacturing a semiconductor device having fine contact hole with high aspect ratio'
[patent_app_type] => 1
[patent_app_number] => 8/910020
[patent_app_country] => US
[patent_app_date] => 1997-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2691
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/114/06114244.pdf
[firstpage_image] =>[orig_patent_app_number] => 910020
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/910020 | Method for manufacturing a semiconductor device having fine contact hole with high aspect ratio | Aug 11, 1997 | Issued |
Array
(
[id] => 4142074
[patent_doc_number] => 06030895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-29
[patent_title] => 'Method of making a soft metal conductor'
[patent_app_type] => 1
[patent_app_number] => 8/902616
[patent_app_country] => US
[patent_app_date] => 1997-07-29
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[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4027
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[pdf_file] => patents/06/030/06030895.pdf
[firstpage_image] =>[orig_patent_app_number] => 902616
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902616 | Method of making a soft metal conductor | Jul 28, 1997 | Issued |
Array
(
[id] => 3942611
[patent_doc_number] => 05946599
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-31
[patent_title] => 'Method of manufacturing a semiconductor IC device'
[patent_app_type] => 1
[patent_app_number] => 8/899668
[patent_app_country] => US
[patent_app_date] => 1997-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2143
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[pdf_file] => patents/05/946/05946599.pdf
[firstpage_image] =>[orig_patent_app_number] => 899668
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/899668 | Method of manufacturing a semiconductor IC device | Jul 23, 1997 | Issued |
Array
(
[id] => 4108194
[patent_doc_number] => 06057248
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[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Method of removing residual contaminants in an alignment mark after a CMP process'
[patent_app_type] => 1
[patent_app_number] => 8/897282
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[patent_app_date] => 1997-07-21
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[pdf_file] => patents/06/057/06057248.pdf
[firstpage_image] =>[orig_patent_app_number] => 897282
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/897282 | Method of removing residual contaminants in an alignment mark after a CMP process | Jul 20, 1997 | Issued |
Array
(
[id] => 4018052
[patent_doc_number] => 05902130
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[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Thermal processing of oxide-compound semiconductor structures'
[patent_app_type] => 1
[patent_app_number] => 8/896234
[patent_app_country] => US
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[pdf_file] => patents/05/902/05902130.pdf
[firstpage_image] =>[orig_patent_app_number] => 896234
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/896234 | Thermal processing of oxide-compound semiconductor structures | Jul 16, 1997 | Issued |
Array
(
[id] => 3969560
[patent_doc_number] => 05904565
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-18
[patent_title] => 'Low resistance contact between integrated circuit metal levels and method for same'
[patent_app_type] => 1
[patent_app_number] => 8/896114
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[patent_app_date] => 1997-07-17
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[pdf_file] => patents/05/904/05904565.pdf
[firstpage_image] =>[orig_patent_app_number] => 896114
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/896114 | Low resistance contact between integrated circuit metal levels and method for same | Jul 16, 1997 | Issued |
Array
(
[id] => 4090778
[patent_doc_number] => 05966629
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Method for fabricating an electrode structure'
[patent_app_type] => 1
[patent_app_number] => 8/892868
[patent_app_country] => US
[patent_app_date] => 1997-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/966/05966629.pdf
[firstpage_image] =>[orig_patent_app_number] => 892868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/892868 | Method for fabricating an electrode structure | Jul 14, 1997 | Issued |
Array
(
[id] => 3967218
[patent_doc_number] => 05956604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide'
[patent_app_type] => 1
[patent_app_number] => 8/889608
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[pdf_file] => patents/05/956/05956604.pdf
[firstpage_image] =>[orig_patent_app_number] => 889608
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/889608 | Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide | Jul 7, 1997 | Issued |
Array
(
[id] => 4071172
[patent_doc_number] => 06069077
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-30
[patent_title] => 'UV resist curing as an indirect means to increase SiN corner selectivity on self-aligned contact etching process'
[patent_app_type] => 1
[patent_app_number] => 8/888636
[patent_app_country] => US
[patent_app_date] => 1997-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/06/069/06069077.pdf
[firstpage_image] =>[orig_patent_app_number] => 888636
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/888636 | UV resist curing as an indirect means to increase SiN corner selectivity on self-aligned contact etching process | Jul 6, 1997 | Issued |
Array
(
[id] => 4039386
[patent_doc_number] => 05926741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Method of forming gate dielectric films for MOSFETs without generation of natural oxide films'
[patent_app_type] => 1
[patent_app_number] => 8/888470
[patent_app_country] => US
[patent_app_date] => 1997-07-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/926/05926741.pdf
[firstpage_image] =>[orig_patent_app_number] => 888470
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/888470 | Method of forming gate dielectric films for MOSFETs without generation of natural oxide films | Jul 6, 1997 | Issued |
| 08/882788 | METHOD FOR MANUFACTURING BUILD-UP MULTI-LAYER PRINTED CIRCUIT BOARD BY USING YAG LASER | Jun 25, 1997 | Abandoned |
Array
(
[id] => 4181614
[patent_doc_number] => 06020260
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[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Method of fabricating a semiconductor device having nitrogen-bearing gate electrode'
[patent_app_type] => 1
[patent_app_number] => 8/882424
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[patent_app_date] => 1997-06-25
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[firstpage_image] =>[orig_patent_app_number] => 882424
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/882424 | Method of fabricating a semiconductor device having nitrogen-bearing gate electrode | Jun 24, 1997 | Issued |
Array
(
[id] => 4107903
[patent_doc_number] => 06057227
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Oxide etch stop techniques for uniform damascene trench depth'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/880580 | Oxide etch stop techniques for uniform damascene trench depth | Jun 22, 1997 | Issued |
Array
(
[id] => 3994463
[patent_doc_number] => 05918141
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[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Method of masking silicide deposition utilizing a photoresist mask'
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[patent_app_number] => 8/879363
[patent_app_country] => US
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[pdf_file] => patents/05/918/05918141.pdf
[firstpage_image] =>[orig_patent_app_number] => 879363
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/879363 | Method of masking silicide deposition utilizing a photoresist mask | Jun 19, 1997 | Issued |
Array
(
[id] => 4236220
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[patent_issue_date] => 2000-12-26
[patent_title] => 'Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/878342 | Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD | Jun 17, 1997 | Issued |
Array
(
[id] => 3937281
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[patent_issue_date] => 1999-06-22
[patent_title] => 'Method for producing deep submicron interconnect vias'
[patent_app_type] => 1
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[pdf_file] => patents/05/915/05915203.pdf
[firstpage_image] =>[orig_patent_app_number] => 872562
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/872562 | Method for producing deep submicron interconnect vias | Jun 9, 1997 | Issued |
Array
(
[id] => 4100490
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[patent_issue_date] => 2000-05-23
[patent_title] => 'Method for forming oxide using high pressure'
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[firstpage_image] =>[orig_patent_app_number] => 868562
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/868562 | Method for forming oxide using high pressure | Jun 3, 1997 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867456 | Method for fabricating metal wire of semiconductor device | Jun 1, 1997 | Issued |
Array
(
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[patent_title] => 'Method for forming bit lines of semiconductor devices'
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[firstpage_image] =>[orig_patent_app_number] => 863148
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/863148 | Method for forming bit lines of semiconductor devices | May 26, 1997 | Issued |