Search

Renee R. Berry

Examiner (ID: 18563)

Most Active Art Unit
2818
Art Unit(s)
2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818
Total Applications
592
Issued Applications
546
Pending Applications
22
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4132151 [patent_doc_number] => 06121158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method for hardening a photoresist material formed on a substrate' [patent_app_type] => 1 [patent_app_number] => 8/910308 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3852 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121158.pdf [firstpage_image] =>[orig_patent_app_number] => 910308 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910308
Method for hardening a photoresist material formed on a substrate Aug 12, 1997 Issued
Array ( [id] => 4155706 [patent_doc_number] => 06114244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for manufacturing a semiconductor device having fine contact hole with high aspect ratio' [patent_app_type] => 1 [patent_app_number] => 8/910020 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2691 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114244.pdf [firstpage_image] =>[orig_patent_app_number] => 910020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910020
Method for manufacturing a semiconductor device having fine contact hole with high aspect ratio Aug 11, 1997 Issued
Array ( [id] => 4142074 [patent_doc_number] => 06030895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method of making a soft metal conductor' [patent_app_type] => 1 [patent_app_number] => 8/902616 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4027 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/030/06030895.pdf [firstpage_image] =>[orig_patent_app_number] => 902616 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902616
Method of making a soft metal conductor Jul 28, 1997 Issued
Array ( [id] => 3942611 [patent_doc_number] => 05946599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method of manufacturing a semiconductor IC device' [patent_app_type] => 1 [patent_app_number] => 8/899668 [patent_app_country] => US [patent_app_date] => 1997-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2143 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946599.pdf [firstpage_image] =>[orig_patent_app_number] => 899668 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899668
Method of manufacturing a semiconductor IC device Jul 23, 1997 Issued
Array ( [id] => 4108194 [patent_doc_number] => 06057248 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method of removing residual contaminants in an alignment mark after a CMP process' [patent_app_type] => 1 [patent_app_number] => 8/897282 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1083 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057248.pdf [firstpage_image] =>[orig_patent_app_number] => 897282 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897282
Method of removing residual contaminants in an alignment mark after a CMP process Jul 20, 1997 Issued
Array ( [id] => 4018052 [patent_doc_number] => 05902130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Thermal processing of oxide-compound semiconductor structures' [patent_app_type] => 1 [patent_app_number] => 8/896234 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2484 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/902/05902130.pdf [firstpage_image] =>[orig_patent_app_number] => 896234 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896234
Thermal processing of oxide-compound semiconductor structures Jul 16, 1997 Issued
Array ( [id] => 3969560 [patent_doc_number] => 05904565 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Low resistance contact between integrated circuit metal levels and method for same' [patent_app_type] => 1 [patent_app_number] => 8/896114 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6548 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904565.pdf [firstpage_image] =>[orig_patent_app_number] => 896114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896114
Low resistance contact between integrated circuit metal levels and method for same Jul 16, 1997 Issued
Array ( [id] => 4090778 [patent_doc_number] => 05966629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Method for fabricating an electrode structure' [patent_app_type] => 1 [patent_app_number] => 8/892868 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5505 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966629.pdf [firstpage_image] =>[orig_patent_app_number] => 892868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892868
Method for fabricating an electrode structure Jul 14, 1997 Issued
Array ( [id] => 3967218 [patent_doc_number] => 05956604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide' [patent_app_type] => 1 [patent_app_number] => 8/889608 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2299 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956604.pdf [firstpage_image] =>[orig_patent_app_number] => 889608 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889608
Ohmic contact to Gallium Arsenide using epitaxially deposited Cobalt Digermanide Jul 7, 1997 Issued
Array ( [id] => 4071172 [patent_doc_number] => 06069077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'UV resist curing as an indirect means to increase SiN corner selectivity on self-aligned contact etching process' [patent_app_type] => 1 [patent_app_number] => 8/888636 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2124 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069077.pdf [firstpage_image] =>[orig_patent_app_number] => 888636 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888636
UV resist curing as an indirect means to increase SiN corner selectivity on self-aligned contact etching process Jul 6, 1997 Issued
Array ( [id] => 4039386 [patent_doc_number] => 05926741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Method of forming gate dielectric films for MOSFETs without generation of natural oxide films' [patent_app_type] => 1 [patent_app_number] => 8/888470 [patent_app_country] => US [patent_app_date] => 1997-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 13422 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926741.pdf [firstpage_image] =>[orig_patent_app_number] => 888470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/888470
Method of forming gate dielectric films for MOSFETs without generation of natural oxide films Jul 6, 1997 Issued
08/882788 METHOD FOR MANUFACTURING BUILD-UP MULTI-LAYER PRINTED CIRCUIT BOARD BY USING YAG LASER Jun 25, 1997 Abandoned
Array ( [id] => 4181614 [patent_doc_number] => 06020260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method of fabricating a semiconductor device having nitrogen-bearing gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/882424 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3183 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020260.pdf [firstpage_image] =>[orig_patent_app_number] => 882424 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/882424
Method of fabricating a semiconductor device having nitrogen-bearing gate electrode Jun 24, 1997 Issued
Array ( [id] => 4107903 [patent_doc_number] => 06057227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Oxide etch stop techniques for uniform damascene trench depth' [patent_app_type] => 1 [patent_app_number] => 8/880580 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5006 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057227.pdf [firstpage_image] =>[orig_patent_app_number] => 880580 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/880580
Oxide etch stop techniques for uniform damascene trench depth Jun 22, 1997 Issued
Array ( [id] => 3994463 [patent_doc_number] => 05918141 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method of masking silicide deposition utilizing a photoresist mask' [patent_app_type] => 1 [patent_app_number] => 8/879363 [patent_app_country] => US [patent_app_date] => 1997-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1503 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918141.pdf [firstpage_image] =>[orig_patent_app_number] => 879363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879363
Method of masking silicide deposition utilizing a photoresist mask Jun 19, 1997 Issued
Array ( [id] => 4236220 [patent_doc_number] => 06165917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD' [patent_app_type] => 1 [patent_app_number] => 8/878342 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4328 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165917.pdf [firstpage_image] =>[orig_patent_app_number] => 878342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878342
Passivation of copper with ammonia-free silicon nitride and application to TFT/LCD Jun 17, 1997 Issued
Array ( [id] => 3937281 [patent_doc_number] => 05915203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method for producing deep submicron interconnect vias' [patent_app_type] => 1 [patent_app_number] => 8/872562 [patent_app_country] => US [patent_app_date] => 1997-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 9 [patent_no_of_words] => 1872 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915203.pdf [firstpage_image] =>[orig_patent_app_number] => 872562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/872562
Method for producing deep submicron interconnect vias Jun 9, 1997 Issued
Array ( [id] => 4100490 [patent_doc_number] => 06066576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-23 [patent_title] => 'Method for forming oxide using high pressure' [patent_app_type] => 1 [patent_app_number] => 8/868562 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3475 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/066/06066576.pdf [firstpage_image] =>[orig_patent_app_number] => 868562 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868562
Method for forming oxide using high pressure Jun 3, 1997 Issued
Array ( [id] => 4034882 [patent_doc_number] => 05856238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Method for fabricating metal wire of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/867456 [patent_app_country] => US [patent_app_date] => 1997-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1093 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856238.pdf [firstpage_image] =>[orig_patent_app_number] => 867456 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/867456
Method for fabricating metal wire of semiconductor device Jun 1, 1997 Issued
Array ( [id] => 4215818 [patent_doc_number] => 06087259 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for forming bit lines of semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/863148 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1834 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087259.pdf [firstpage_image] =>[orig_patent_app_number] => 863148 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863148
Method for forming bit lines of semiconductor devices May 26, 1997 Issued
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