
Renee R. Berry
Examiner (ID: 18563)
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818 |
| Total Applications | 592 |
| Issued Applications | 546 |
| Pending Applications | 22 |
| Abandoned Applications | 24 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3999798
[patent_doc_number] => 05950107
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'In-situ pre-ILD deposition treatment to improve ILD to metal adhesion'
[patent_app_type] => 1
[patent_app_number] => 8/768916
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 21
[patent_no_of_words] => 4978
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/950/05950107.pdf
[firstpage_image] =>[orig_patent_app_number] => 768916
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768916 | In-situ pre-ILD deposition treatment to improve ILD to metal adhesion | Dec 16, 1996 | Issued |
Array
(
[id] => 4070123
[patent_doc_number] => 05933753
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Open-bottomed via liner structure and method for fabricating same'
[patent_app_type] => 1
[patent_app_number] => 8/767572
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3015
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/933/05933753.pdf
[firstpage_image] =>[orig_patent_app_number] => 767572
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767572 | Open-bottomed via liner structure and method for fabricating same | Dec 15, 1996 | Issued |
Array
(
[id] => 4215804
[patent_doc_number] => 06087258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Method for circuitizing through-holes by photo-activated seeding'
[patent_app_type] => 1
[patent_app_number] => 8/764001
[patent_app_country] => US
[patent_app_date] => 1996-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 6152
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/087/06087258.pdf
[firstpage_image] =>[orig_patent_app_number] => 764001
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/764001 | Method for circuitizing through-holes by photo-activated seeding | Dec 11, 1996 | Issued |
Array
(
[id] => 4016828
[patent_doc_number] => 05924009
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Titanium silicide interconnect method'
[patent_app_type] => 1
[patent_app_number] => 8/762030
[patent_app_country] => US
[patent_app_date] => 1996-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2183
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/924/05924009.pdf
[firstpage_image] =>[orig_patent_app_number] => 762030
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/762030 | Titanium silicide interconnect method | Dec 10, 1996 | Issued |
| 08/704714 | ELECTRIC CONNECTIONS ARRANGED IN A HIGH-DENSITY GRID | Dec 8, 1996 | Abandoned |
Array
(
[id] => 3815692
[patent_doc_number] => 05770520
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Method of making a barrier layer for via or contact opening of integrated circuit structure'
[patent_app_type] => 1
[patent_app_number] => 8/760466
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3291
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/770/05770520.pdf
[firstpage_image] =>[orig_patent_app_number] => 760466
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760466 | Method of making a barrier layer for via or contact opening of integrated circuit structure | Dec 4, 1996 | Issued |
Array
(
[id] => 4031419
[patent_doc_number] => 05963836
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Methods for minimizing as-deposited stress in tungsten silicide films'
[patent_app_type] => 1
[patent_app_number] => 8/759868
[patent_app_country] => US
[patent_app_date] => 1996-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4867
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/963/05963836.pdf
[firstpage_image] =>[orig_patent_app_number] => 759868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759868 | Methods for minimizing as-deposited stress in tungsten silicide films | Dec 2, 1996 | Issued |
Array
(
[id] => 3771867
[patent_doc_number] => 05807787
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation'
[patent_app_type] => 1
[patent_app_number] => 8/755862
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4046
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/807/05807787.pdf
[firstpage_image] =>[orig_patent_app_number] => 755862
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/755862 | Method for reducing surface leakage current on semiconductor intergrated circuits during polyimide passivation | Dec 1, 1996 | Issued |
Array
(
[id] => 3771882
[patent_doc_number] => 05807788
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Method for selective deposition of refractory metal and device formed thereby'
[patent_app_type] => 1
[patent_app_number] => 8/753128
[patent_app_country] => US
[patent_app_date] => 1996-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3938
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/807/05807788.pdf
[firstpage_image] =>[orig_patent_app_number] => 753128
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/753128 | Method for selective deposition of refractory metal and device formed thereby | Nov 19, 1996 | Issued |
Array
(
[id] => 3804767
[patent_doc_number] => 05830805
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Electroless deposition equipment or apparatus and method of performing electroless deposition'
[patent_app_type] => 1
[patent_app_number] => 8/751631
[patent_app_country] => US
[patent_app_date] => 1996-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4643
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/830/05830805.pdf
[firstpage_image] =>[orig_patent_app_number] => 751631
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/751631 | Electroless deposition equipment or apparatus and method of performing electroless deposition | Nov 17, 1996 | Issued |
Array
(
[id] => 4031478
[patent_doc_number] => 05963840
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-05
[patent_title] => 'Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions'
[patent_app_type] => 1
[patent_app_number] => 8/748960
[patent_app_country] => US
[patent_app_date] => 1996-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 54
[patent_no_of_words] => 42921
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/963/05963840.pdf
[firstpage_image] =>[orig_patent_app_number] => 748960
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/748960 | Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions | Nov 12, 1996 | Issued |
Array
(
[id] => 4286863
[patent_doc_number] => 06211080
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Repair of dielectric-coated electrode or circuit defects'
[patent_app_type] => 1
[patent_app_number] => 8/741480
[patent_app_country] => US
[patent_app_date] => 1996-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 2248
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/211/06211080.pdf
[firstpage_image] =>[orig_patent_app_number] => 741480
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741480 | Repair of dielectric-coated electrode or circuit defects | Oct 29, 1996 | Issued |
Array
(
[id] => 4156260
[patent_doc_number] => 06156645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Method of forming a metal layer on a substrate, including formation of wetting layer at a high temperature'
[patent_app_type] => 1
[patent_app_number] => 8/740290
[patent_app_country] => US
[patent_app_date] => 1996-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 7799
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156645.pdf
[firstpage_image] =>[orig_patent_app_number] => 740290
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/740290 | Method of forming a metal layer on a substrate, including formation of wetting layer at a high temperature | Oct 24, 1996 | Issued |
Array
(
[id] => 4102512
[patent_doc_number] => 06051477
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/734920
[patent_app_country] => US
[patent_app_date] => 1996-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 2199
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/051/06051477.pdf
[firstpage_image] =>[orig_patent_app_number] => 734920
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/734920 | Method of fabricating semiconductor device | Oct 21, 1996 | Issued |
Array
(
[id] => 3825813
[patent_doc_number] => 05783486
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Bridge-free self aligned silicide process'
[patent_app_type] => 1
[patent_app_number] => 8/734066
[patent_app_country] => US
[patent_app_date] => 1996-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3250
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/783/05783486.pdf
[firstpage_image] =>[orig_patent_app_number] => 734066
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/734066 | Bridge-free self aligned silicide process | Oct 17, 1996 | Issued |
Array
(
[id] => 4018117
[patent_doc_number] => 05902135
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Method for removing crystal defects in silicon wafers'
[patent_app_type] => 1
[patent_app_number] => 8/730878
[patent_app_country] => US
[patent_app_date] => 1996-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 792
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/902/05902135.pdf
[firstpage_image] =>[orig_patent_app_number] => 730878
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730878 | Method for removing crystal defects in silicon wafers | Oct 17, 1996 | Issued |
Array
(
[id] => 4000896
[patent_doc_number] => 05858854
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-12
[patent_title] => 'Method for forming high contrast alignment marks'
[patent_app_type] => 1
[patent_app_number] => 8/730382
[patent_app_country] => US
[patent_app_date] => 1996-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 3010
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 427
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/858/05858854.pdf
[firstpage_image] =>[orig_patent_app_number] => 730382
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730382 | Method for forming high contrast alignment marks | Oct 15, 1996 | Issued |
Array
(
[id] => 4146221
[patent_doc_number] => 06063707
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Selective PVD growth of copper on patterned structures by selectively resputtering and sputtering areas of a substrate'
[patent_app_type] => 1
[patent_app_number] => 8/730038
[patent_app_country] => US
[patent_app_date] => 1996-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1606
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/063/06063707.pdf
[firstpage_image] =>[orig_patent_app_number] => 730038
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730038 | Selective PVD growth of copper on patterned structures by selectively resputtering and sputtering areas of a substrate | Oct 10, 1996 | Issued |
Array
(
[id] => 3999713
[patent_doc_number] => 05950103
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Manufacture of dielectric oxide lamination structure and electronic circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/726174
[patent_app_country] => US
[patent_app_date] => 1996-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 4524
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/950/05950103.pdf
[firstpage_image] =>[orig_patent_app_number] => 726174
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/726174 | Manufacture of dielectric oxide lamination structure and electronic circuit device | Oct 3, 1996 | Issued |
Array
(
[id] => 4016865
[patent_doc_number] => 05924012
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Methods, complexes, and system for forming metal-containing films'
[patent_app_type] => 1
[patent_app_number] => 8/725064
[patent_app_country] => US
[patent_app_date] => 1996-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5985
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/924/05924012.pdf
[firstpage_image] =>[orig_patent_app_number] => 725064
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/725064 | Methods, complexes, and system for forming metal-containing films | Oct 1, 1996 | Issued |